From 9f0df97afb590e40479e33806208870ad331467c Mon Sep 17 00:00:00 2001 From: David Daney Date: Tue, 7 Sep 2004 19:39:06 +0000 Subject: [PATCH] config.gcc: Added support for --with-divide=[breaks|traps] for mips targets. 2004-09-07 David Daney * config.gcc: Added support for --with-divide=[breaks|traps] for mips targets. * config/mips/mips.h (MASK_DIVIDE_BREAKS): New target_flags bit. (TARGET_DIVIDE_TRAPS): New macro. (TARGET_SWITCHES): Added -mdivide-traps and -mdivide-breaks. (OPTION_DEFAULT_SPECS): Added --with-divide= support. * config/mips/mips.c (mips_idiv_insns): Generate proper count on GENERATE_DIVIDE_TRAPS. (mips_output_division): Emit conditional trap if GENERATE_DIVIDE_TRAPS is set. * doc/install.texi: Document --with-divide. * doc/invoke.texi: Document -mdivide-traps and -mdivide-breaks. From-SVN: r87153 --- gcc/ChangeLog | 15 +++++++++++++++ gcc/config.gcc | 13 +++++++++++-- gcc/config/mips/mips.c | 13 ++++++++++++- gcc/config/mips/mips.h | 18 +++++++++++++++--- gcc/doc/install.texi | 22 ++++++++++++++++++++++ gcc/doc/invoke.texi | 18 ++++++++++++++++++ 6 files changed, 93 insertions(+), 6 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 732e7885d6f..476069b3d4f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2004-09-07 David Daney + + * config.gcc: Added support for --with-divide=[breaks|traps] for + mips targets. + * config/mips/mips.h (MASK_DIVIDE_BREAKS): New target_flags bit. + (TARGET_DIVIDE_TRAPS): New macro. + (TARGET_SWITCHES): Added -mdivide-traps and -mdivide-breaks. + (OPTION_DEFAULT_SPECS): Added --with-divide= support. + * config/mips/mips.c (mips_idiv_insns): Generate proper count on + GENERATE_DIVIDE_TRAPS. + (mips_output_division): Emit conditional trap if + GENERATE_DIVIDE_TRAPS is set. + * doc/install.texi: Document --with-divide. + * doc/invoke.texi: Document -mdivide-traps and -mdivide-breaks. + 2004-09-07 Caroline Tice * cfgrtl.c (rtl_verify_flow_info_1): Add new edge flag, diff --git a/gcc/config.gcc b/gcc/config.gcc index 4f955a02b62..3c5b8458356 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -2425,7 +2425,7 @@ fi ;; mips*-*-*) - supported_defaults="abi arch float tune" + supported_defaults="abi arch float tune divide" case ${with_float} in "" | soft | hard) @@ -2446,6 +2446,15 @@ fi exit 1 ;; esac + + case ${with_divide} in + "" | breaks | traps) + # OK + ;; + *) + echo "Unknown division check type use in --with-divide=$with_divide" 1>&2 + exit 1 + esac ;; powerpc*-*-* | rs6000-*-*) @@ -2687,7 +2696,7 @@ fi esac t= - all_defaults="abi cpu arch tune schedule float mode fpu" + all_defaults="abi cpu arch tune schedule float mode fpu divide" for option in $all_defaults do eval "val=\$with_$option" diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 5f7e149e167..ea0eb7b41f3 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -1375,7 +1375,13 @@ mips_idiv_insns (void) count = 1; if (TARGET_CHECK_ZERO_DIV) - count += 2; + { + if (GENERATE_DIVIDE_TRAPS) + count++; + else + count += 2; + } + if (TARGET_FIX_R4000 || TARGET_FIX_R4400) count++; return count; @@ -8805,6 +8811,11 @@ mips_output_division (const char *division, rtx *operands) output_asm_insn (s, operands); s = "bnez\t%2,1f\n\tbreak\t7\n1:"; } + else if (GENERATE_DIVIDE_TRAPS) + { + output_asm_insn (s, operands); + s = "teq\t%2,%.,7"; + } else { output_asm_insn ("%(bne\t%2,%.,1f", operands); diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 8862e5816b6..f9104bdff4d 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -160,7 +160,8 @@ extern const struct mips_cpu_info *mips_tune_info; #define MASK_FIX_VR4120 0x01000000 /* Work around VR4120 errata. */ #define MASK_VR4130_ALIGN 0x02000000 /* Perform VR4130 alignment opts. */ #define MASK_FP_EXCEPTIONS 0x04000000 /* FP exceptions are enabled. */ - +#define MASK_DIVIDE_BREAKS 0x08000000 /* Divide by zero check uses + break instead of trap. */ #define MASK_PAIRED_SINGLE 0x10000000 /* Support paired-single FPU. */ #define MASK_MIPS3D 0x20000000 /* Support MIPS-3D instructions. */ @@ -222,6 +223,7 @@ extern const struct mips_cpu_info *mips_tune_info; #define TARGET_4300_MUL_FIX ((target_flags & MASK_4300_MUL_FIX) != 0) #define TARGET_CHECK_ZERO_DIV ((target_flags & MASK_NO_CHECK_ZERO_DIV) == 0) +#define TARGET_DIVIDE_TRAPS ((target_flags & MASK_DIVIDE_BREAKS) == 0) #define TARGET_BRANCHLIKELY ((target_flags & MASK_BRANCHLIKELY) != 0) @@ -632,6 +634,10 @@ extern const struct mips_cpu_info *mips_tune_info; N_("Trap on integer divide by zero")}, \ {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \ N_("Don't trap on integer divide by zero")}, \ + {"divide-traps", -MASK_DIVIDE_BREAKS, \ + N_("Use trap to check for integer divide by zero")}, \ + {"divide-breaks", MASK_DIVIDE_BREAKS, \ + N_("Use break to check for integer divide by zero")}, \ { "branch-likely", MASK_BRANCHLIKELY, \ N_("Use Branch Likely instructions, overriding default for arch")}, \ { "no-branch-likely", -MASK_BRANCHLIKELY, \ @@ -782,13 +788,19 @@ extern const struct mips_cpu_info *mips_tune_info; --with-tune is ignored if -mtune is specified. --with-abi is ignored if -mabi is specified. --with-float is ignored if -mhard-float or -msoft-float are - specified. */ + specified. + --with-divide is ignored if -mdivide-traps or -mdivide-breaks are + specified. */ #define OPTION_DEFAULT_SPECS \ {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \ {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ - {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" } + {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \ + {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" } + +#define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \ + && ISA_HAS_COND_TRAP) #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \ && !TARGET_SR71K \ diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index dfad815d49a..01cbb47c25b 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -959,6 +959,18 @@ options and for @option{-mhard-float} or @option{-msoft-float}. As with @option{--with-cpu}, which switches will be accepted and acceptable values of the arguments depend on the target. +@item --with-divide=@var{type} +Specify how the compiler should generate code for checking for +division by zero. This option is only supported on the MIPS target. +The possibilities for @var{type} are: +@table @code +@item traps +Division by zero checks use conditional traps (this is the default on +systems that support conditional traps). +@item breaks +Division by zero checks use the break instruction. +@end table + @item --enable-altivec Specify that the target supports AltiVec vector enhancements. This option will adjust the ABI for AltiVec enhancements, as well as generate @@ -3201,6 +3213,16 @@ configure for @samp{mipsel-elf} as a workaround. The @samp{mips*-*-linux*} target continues to use the MIPS II routines. More work on this is expected in future releases. +MIPS systems check for division by zero (unless +@option{-mno-check-zero-division} is passed to the compiler) by +generating either a conditional trap or a break instruction. Using +trap results in smaller code, but is only supported on MIPS II and +later. Also, some versions of the Linux kernel have a bug that +prevents trap from generating the proper signal (SIGFPE). To enable +the use of break, use the @option{--with-divide=breaks} +@command{configure} option when configuring GCC. The default is to +use traps on systems that support them. + Cross-compilers for the Mips as target using the Mips assembler currently do not work, because the auxiliary programs @file{mips-tdump.c} and @file{mips-tfile.c} can't be compiled on diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ea5f983a768..b757e269c27 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -545,6 +545,7 @@ Objective-C and Objective-C++ Dialects}. -msplit-addresses -mno-split-addresses @gol -mexplicit-relocs -mno-explicit-relocs @gol -mcheck-zero-division -mno-check-zero-division @gol +-mdivide-traps -mdivide-breaks @gol -mmemcpy -mno-memcpy -mlong-calls -mno-long-calls @gol -mmad -mno-mad -mfused-madd -mno-fused-madd -nocpp @gol -mfix-r4000 -mno-fix-r4000 -mfix-r4400 -mno-fix-r4400 @gol @@ -9500,6 +9501,23 @@ to use an assembler that supports relocation operators. Trap (do not trap) on integer division by zero. The default is @option{-mcheck-zero-division}. +@item -mdivide-traps +@itemx -mdivide-breaks +@opindex mdivide-traps +@opindex mdivide-breaks +MIPS systems check for division by zero by generating either a +conditional trap or a break instruction. Using traps results in +smaller code, but is only supported on MIPS II and later. Also, some +versions of the Linux kernel have a bug that prevents trap from +generating the proper signal (SIGFPE). Use @option{-mdivide-traps} to +allow conditional traps on architectures that support them and +@option{-mdivide-breaks} to force the use of breaks. + +The default is usually @option{-mdivide-traps}, but this can be +overridden at configure time using @option{--with-divide=breaks}. +Divide-by-zero checks can be completely disabled using +@option{-mno-check-zero-division}. + @item -mmemcpy @itemx -mno-memcpy @opindex mmemcpy -- 2.30.2