From 9f33eab664703a6537c0eea7dee43a0d0f116d33 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 16 Jun 2020 18:16:53 +0100 Subject: [PATCH] add ports to TestMemory --- src/soc/experiment/testmem.py | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/soc/experiment/testmem.py b/src/soc/experiment/testmem.py index 7c753a0d..4821e21d 100644 --- a/src/soc/experiment/testmem.py +++ b/src/soc/experiment/testmem.py @@ -17,3 +17,14 @@ class TestMemory(Elaboratable): m.submodules.rdport = self.rdport m.submodules.wrport = self.wrport return m + + def __iter__(self): + yield self.rdport.addr + yield self.rdport.data + yield self.rdport.en + yield self.wrport.addr + yield self.wrport.data + yield self.wrport.en + + def ports(self): + return list(self) -- 2.30.2