From 9f3ed1726ea82d18b5f3410fd60d3a96c652f447 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 11:15:16 -0700 Subject: [PATCH] pmgen to also iterate over all module ports --- passes/pmgen/pmgen.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 18c3bf5a5..8944ac2bf 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -390,8 +390,6 @@ with open(outfile, "w") as f: print(" void add_siguser(const SigSpec &sig, Cell *cell) {", file=f) print(" for (auto bit : sigmap(sig)) {", file=f) print(" if (bit.wire == nullptr) continue;", file=f) - print(" if (sigusers.count(bit) == 0 && bit.wire->port_id)", file=f) - print(" sigusers[bit].insert(nullptr);", file=f) print(" sigusers[bit].insert(cell);", file=f) print(" }", file=f) print(" }", file=f) @@ -450,6 +448,10 @@ with open(outfile, "w") as f: print(" for (auto &conn : cell->connections())", file=f) print(" add_siguser(conn.second, cell);", file=f) print(" }", file=f) + print(" for (auto port : module->ports)", file=f) + print(" add_siguser(module->wire(port), nullptr);", file=f) + print(" ", file=f) + print(" for (auto cell : cells) {", file=f) for index in range(len(blocks)): -- 2.30.2