From 9f3f2f99c48f3f18fb3b0978118adbdec3f627ea Mon Sep 17 00:00:00 2001 From: "Samuel A. Falvo II" Date: Mon, 3 Aug 2020 08:17:55 -0700 Subject: [PATCH] WIP: check MB > ME and select mask appropriately --- src/soc/fu/shift_rot/formal/proof_main_stage.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py index fa1674f3..2f0455f4 100644 --- a/src/soc/fu/shift_rot/formal/proof_main_stage.py +++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py @@ -185,7 +185,10 @@ class Driver(Elaboratable): # code norms. mrl = Signal(64, reset_less=True, name='MASK_FOR_RLC') - comb += mrl.eq(ml | mr) + with m.If(mb > me): + comb += mrl.eq(ml | mr) + with m.Else(): + comb += mrl.eq(ml & mr) ainp = Signal(64, reset_less=True, name='A_INP_FOR_RLC') comb += ainp.eq(field(a, 32, 63)) -- 2.30.2