From 9f4b4d23f44a395e0c5766e156f2647a13f52c37 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 3 Jul 2023 20:20:55 -0700 Subject: [PATCH] change rest of int/fp conversion docs to use new P/S/E-type naming --- .../sv/int_fp_mv/cvt_fp_to_int_overview.mdwn | 6 ++-- .../sv/int_fp_mv/moves_and_conversions.mdwn | 32 +++++++++---------- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/openpower/sv/int_fp_mv/cvt_fp_to_int_overview.mdwn b/openpower/sv/int_fp_mv/cvt_fp_to_int_overview.mdwn index f2c05222b..699315b90 100644 --- a/openpower/sv/int_fp_mv/cvt_fp_to_int_overview.mdwn +++ b/openpower/sv/int_fp_mv/cvt_fp_to_int_overview.mdwn @@ -7,11 +7,11 @@ or out-of-range floating-point value to integer, so different programming languages and ISAs have made different choices. The different conversion modes supported by the `cffpr` instruction are as follows: -* P-Type: +* P-Type:
This type of conversion is that used by most other PowerISA instructions, as well as commonly used floating-point to integer conversions on x86. -* S-Type: +* S-Type:
This type of conversion is used for WebAssembly's [`trunc_sat_u`](https://webassembly.github.io/spec/core/exec/numerics.html#op-trunc-sat-u) and @@ -29,7 +29,7 @@ modes supported by the `cffpr` instruction are as follows: instructions when decorated with [the `SaturatedConversion` decorator](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#_a_id_decoration_a_decoration). -* E-Type: +* E-Type:
This type of conversion is used for [ECMAScript's `ToInt32` abstract operation](https://262.ecma-international.org/14.0/#sec-toint32). diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn index fb0aeae36..378022d43 100644 --- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn +++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn @@ -15,19 +15,19 @@ Tables that are used by ## `CVM` -- Float to Integer Conversion Mode -| `CVM` | `rounding_mode` | Semantics | -|-------|-----------------|----------------------------------| -| 000 | from `FPSCR` | [OpenPower semantics] | -| 001 | Truncate | [OpenPower semantics] | -| 010 | from `FPSCR` | [Java/Saturating semantics] | -| 011 | Truncate | [Java/Saturating semantics] | -| 100 | from `FPSCR` | [JavaScript semantics] | -| 101 | Truncate | [JavaScript semantics] | -| rest | -- | illegal instruction trap for now | - -[OpenPower semantics]: #fp-to-int-openpower-conversion-semantics -[Java/Saturating semantics]: #fp-to-int-java-saturating-conversion-semantics -[JavaScript semantics]: #fp-to-int-javascript-conversion-semantics +| `CVM` | `rounding_mode` | Semantics | +|-------|-----------------|-----------| +| 000 | from `FPSCR` | [P-Type] | +| 001 | Truncate | [P-Type] | +| 010 | from `FPSCR` | [S-Type] | +| 011 | Truncate | [S-Type] | +| 100 | from `FPSCR` | [E-Type] | +| 101 | Truncate | [E-Type] | +| rest | -- | invalid | + +[P-Type]: #fpr-to-gpr-conversion-p-type +[S-Type]: #fpr-to-gpr-conversion-s-type +[E-Type]: #fpr-to-gpr-conversion-e-type ---------- @@ -368,7 +368,7 @@ Special Registers altered: rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src) switch(CVM) - case(0, 1): # OpenPower semantics + case(0, 1): # P-Type if IsNaN(rnd) then result <- si64_CONVERT_FROM_BFP(range_min) else if bfp_COMPARE_GT(rnd, range_max) then @@ -379,7 +379,7 @@ Special Registers altered: result <- ui64_CONVERT_FROM_BFP(rnd) else # Signed 32/64-bit result <- si64_CONVERT_FROM_BFP(rnd) - case(2, 3): # Java/Saturating semantics + case(2, 3): # S-Type if IsNaN(rnd) then result <- [0] * 64 else if bfp_COMPARE_GT(rnd, range_max) then @@ -390,7 +390,7 @@ Special Registers altered: result <- ui64_CONVERT_FROM_BFP(rnd) else # Signed 32/64-bit result <- si64_CONVERT_FROM_BFP(rnd) - default: # JavaScript semantics + default: # E-Type # CVM = 6, 7 are illegal instructions # using a 128-bit intermediate works here because the largest type # this instruction can convert from has 53 significand bits, and -- 2.30.2