From 9f4ecf57de1313c940bea497ac445a63abded294 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 20 Jun 2022 21:01:56 +0100 Subject: [PATCH] nope. more repeated stuff, removed --- svp64-primer/summary.tex | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex index 9a9f75f60..d71686a80 100644 --- a/svp64-primer/summary.tex +++ b/svp64-primer/summary.tex @@ -178,24 +178,12 @@ Advantages include: \begin{itemize} \item Easy to create first (and sometimes only) implementation as a literal for-loop in hardware, simulators, and compilers. - \item Hardware Architects may understand and implement SV as - being an extra pipeline stage, inserted between decode and - issue. Essentially a simple for-loop issuing element-level - sub-instructions. - \item More complex HDL can be done by repeating existing scalar - ALUs and pipelines as blocks, leveraging existing Multi-Issue - Infrastructure. - \item Mostly high-level "context" which does not significantly - deviate from scalar Power ISA and, in its purest form - being a "for-loop around scalar instructions". Thus SV is - minimally-disruptive and consequently has a reasonable chance - of broad community adoption and acceptance. \item Obliterates SIMD opcode proliferation ($O(N^6)$) as well as dedicated Vectorisation ISAs. No more separate vector instructions. \item Reducing maintenance overhead (no separate Vector instructions). - Adding a Scalar instruction automatically gains a Vectorised - version. + Adding any new Scalar instruction + \textit{automatically adds a Vectorised version of the same}. \item Easier for compilers, coders, documentation \end{itemize} -- 2.30.2