From 9f636f79853779d008cdd94898f563dbb7790bf7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 27 Feb 2015 10:47:54 +0100 Subject: [PATCH] move memtest to sdram --- misoclib/gensoc/__init__.py | 3 ++- misoclib/{ => sdram}/memtest/__init__.py | 0 2 files changed, 2 insertions(+), 1 deletion(-) rename misoclib/{ => sdram}/memtest/__init__.py (100%) diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py index 332310c4..1e99d20a 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/gensoc/__init__.py @@ -6,9 +6,10 @@ from migen.bank import csrgen from migen.bus import wishbone, csr, lasmibus, dfi from migen.bus import wishbone2lasmi, wishbone2csr -from misoclib import lm32, mor1kx, uart, identifier, timer, memtest +from misoclib import lm32, mor1kx, uart, identifier, timer from misoclib.sdram import lasmicon from misoclib.sdram import dfii +from misoclib.sdram import memtest from misoclib.sdram.minicon import Minicon def mem_decoder(address, start=26, end=29): diff --git a/misoclib/memtest/__init__.py b/misoclib/sdram/memtest/__init__.py similarity index 100% rename from misoclib/memtest/__init__.py rename to misoclib/sdram/memtest/__init__.py -- 2.30.2