From 9f65481b077e2b354c48c65c3fc46fef379577ae Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 16 Apr 2018 01:58:27 +0100 Subject: [PATCH] add comparison section --- simple_v_extension.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index bd5c1502e..c9308e28f 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -1114,7 +1114,7 @@ RVV (as it stands, Draft 0.4 Section 17, RISC-V ISA V2.3-Draft) transferred out to memory, into standard regfiles, then back to memory, then back to the vector unit, this to occur potentially multiple times. * minus: will never fit into Compressed instruction space (as-is. May - be able to do so if features of Simple-V are partially adopted). + be able to do so if "indirect" features of Simple-V are partially adopted). * plus-and-slight-minus: extended variants may address up to 256 vectorised registers (requires 48/64-bit opcodes to do it). -- 2.30.2