From 9f887b7634e3ec299e2c0b8ac8b982f7c99f9622 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 30 Aug 2020 01:38:47 -0700 Subject: [PATCH] mips,cpu: Get rid of the IsIprAccess StaticInst flag. This was set by MIPS in two places, I think largely just because it was available. This flag refers to IPRs which are an Alpha concept. In the O3 CPU, IsIprAccess was used as a possible indicator to determine if an instruction IsSerializeBefore, but we've already got a flag for that. In the minor CPU, which hasn't been made to work with MIPS as far as I know, it was used in a condition but not mentioned in the comment alongside the condition. I think there it was added for the sake of Alpha. This change eliminates that flag and removes it from the O3 and minor CPUs. In the MIPS ISA description, the instructions that were marked as IsIprAccess have now been marked as IsSerializeBefore since, if there was a real reason for them to be marked as IsIprAccess, it would have been to get it them to work in O3, and there IsSerializeBefore gets equivalent behavior. Change-Id: Ia874cde12fa70b998d3e638458f13d69798d40b7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33739 Maintainer: Gabe Black Tested-by: kokoro Reviewed-by: Jason Lowe-Power --- src/arch/mips/isa/decoder.isa | 4 ++-- src/cpu/StaticInstFlags.py | 1 - src/cpu/base_dyn_inst.hh | 1 - src/cpu/minor/execute.cc | 3 +-- src/cpu/o3/rename_impl.hh | 3 +-- src/cpu/static_inst.hh | 1 - 6 files changed, 4 insertions(+), 9 deletions(-) diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 76453b09f..73e2b5dc8 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -174,10 +174,10 @@ decode OPCODE_HI default Unknown::unknown() { 0x2: decode FUNCTION_LO { 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, - IntMultOp, IsIprAccess); + IntMultOp, IsSerializeBefore); 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, - IntMultOp, IsIprAccess); + IntMultOp, IsSerializeBefore); 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); } diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py index b70f919b0..151074edc 100644 --- a/src/cpu/StaticInstFlags.py +++ b/src/cpu/StaticInstFlags.py @@ -89,7 +89,6 @@ class StaticInstFlags(Enum): 'IsNonSpeculative', # Should not be executed speculatively 'IsQuiesce', # Is a quiesce instruction - 'IsIprAccess', # Accesses IPRs 'IsUnverifiable', # Can't be verified by a checker 'IsSyscall', # Causes a system call to be emulated in syscall diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index bfe0492f8..00639ad8e 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -557,7 +557,6 @@ class BaseDynInst : public ExecContext, public RefCounted bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } bool isQuiesce() const { return staticInst->isQuiesce(); } - bool isIprAccess() const { return staticInst->isIprAccess(); } bool isUnverifiable() const { return staticInst->isUnverifiable(); } bool isSyscall() const { return staticInst->isSyscall(); } bool isMacroop() const { return staticInst->isMacroop(); } diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc index 45ca00233..f8db5231a 100644 --- a/src/cpu/minor/execute.cc +++ b/src/cpu/minor/execute.cc @@ -224,8 +224,7 @@ Execute::tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch) !inst->isFault() && inst->isLastOpInInst() && (inst->staticInst->isSerializeAfter() || - inst->staticInst->isSquashAfter() || - inst->staticInst->isIprAccess()); + inst->staticInst->isSquashAfter()); DPRINTF(Branch, "tryToBranch before: %s after: %s%s\n", pc_before, target, (force_branch ? " (forcing)" : "")); diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 1cbe87a56..052012ee2 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -684,8 +684,7 @@ DefaultRename::renameInsts(ThreadID tid) // instructions. This is mainly due to lack of support for // out-of-order operations of either of those classes of // instructions. - if ((inst->isIprAccess() || inst->isSerializeBefore()) && - !inst->isSerializeHandled()) { + if (inst->isSerializeBefore() && !inst->isSerializeHandled()) { DPRINTF(Rename, "Serialize before instruction encountered.\n"); if (!inst->isTempSerializeBefore()) { diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index e536b8412..353c0e358 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -190,7 +190,6 @@ class StaticInst : public RefCounted, public StaticInstFlags bool isWriteBarrier() const { return flags[IsWriteBarrier]; } bool isNonSpeculative() const { return flags[IsNonSpeculative]; } bool isQuiesce() const { return flags[IsQuiesce]; } - bool isIprAccess() const { return flags[IsIprAccess]; } bool isUnverifiable() const { return flags[IsUnverifiable]; } bool isSyscall() const { return flags[IsSyscall]; } bool isMacroop() const { return flags[IsMacroop]; } -- 2.30.2