From 9f98bf78f8a86716ebb07fac9c5a9e110577652d Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Fri, 27 Aug 2021 14:07:08 +0100
Subject: [PATCH]

---
 openpower/sv/branches.mdwn | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index e28942af0..c2a2a09df 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -230,6 +230,9 @@ for srcstep in range(VL):
         testbit = CRbits[BI & 0b11]
         # testbit = CR[BI+32+srcstep*4]
     else if not SVRMmode.sz:
+      # inverted CTR test skip mode
+      if ¬BO[2] & CTRtest & ¬CTI then
+         CTR = CTR - 1
         continue
     else
         testbit = SVRMmode.SNZ
@@ -270,6 +273,9 @@ if predicate[srcstep]:
         CR{SVCRf+srcstep} = CRbits
     testbit = CRbits[BI & 0b11]
 else if not SVRMmode.sz:
+    # inverted CTR test skip mode
+    if ¬BO[2] & CTRtest & ¬CTI then
+       CTR = CTR - 1
     SVSTATE.srcstep = new_srcstep
     exit # no branch testing
 else
@@ -291,7 +297,7 @@ if (mode_is_64bit) then M <- 0
 else M <- 32
 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
 ctrdec = ¬BO[2]
-if CSk & (cond_ok ^ CTi) then
+if CTRtest & (cond_ok ^ CTi) then
    ctrdec = 0b0
 if ctrdec then CTR <- CTR - 1
 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
-- 
2.30.2