From 9f9cb4b8ffe9f24f84ff3a5d5de79e69c92f687e Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 9 Sep 2022 13:27:33 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001/discussion.mdwn | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openpower/sv/rfc/ls001/discussion.mdwn b/openpower/sv/rfc/ls001/discussion.mdwn index 9cc97f6e5..10cc182fd 100644 --- a/openpower/sv/rfc/ls001/discussion.mdwn +++ b/openpower/sv/rfc/ls001/discussion.mdwn @@ -10,6 +10,10 @@ although the "penalty" is that any such "escape-sequenced" 32-bit instructions require a prefix-marker bit, it does effectively double the **entirety** of the 32-bit Major Opcode space. +this "doubling" is already public and part of EXT001, the idea +here is to mirror that (bit 6), but unlike EXT001, use bit 7 +to mark whether the instruction is SVP64-vector or SVP64-single. + | 0-5 | 6 | 7 | 8-31 | Description | |-----|---|---|------|---------------------------| | PO | 0 | 0 | nnnn | new, scalar (SVP64Single) | -- 2.30.2