From 9fa9bdcf6850ddc0c3bd39fae593ed3f33207111 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 7 Apr 2016 08:56:53 +0200 Subject: [PATCH] build/sim: adapt verilator simulation to new stream signals --- litex/boards/platforms/sim.py | 16 +++++++------- litex/build/sim/dut_tb.cpp | 38 ++++++++++++++++----------------- litex/build/sim/verilator.py | 40 +++++++++++++++++------------------ litex/soc/cores/uart/core.py | 8 +++---- 4 files changed, 51 insertions(+), 51 deletions(-) diff --git a/litex/boards/platforms/sim.py b/litex/boards/platforms/sim.py index 8b099184..6860fde0 100644 --- a/litex/boards/platforms/sim.py +++ b/litex/boards/platforms/sim.py @@ -10,24 +10,24 @@ _io = [ ("sys_clk", 0, SimPins(1)), ("sys_rst", 0, SimPins(1)), ("serial", 0, - Subsignal("source_stb", SimPins(1)), - Subsignal("source_ack", SimPins(1)), + Subsignal("source_valid", SimPins(1)), + Subsignal("source_ready", SimPins(1)), Subsignal("source_data", SimPins(8)), - Subsignal("sink_stb", SimPins(1)), - Subsignal("sink_ack", SimPins(1)), + Subsignal("sink_valid", SimPins(1)), + Subsignal("sink_ready", SimPins(1)), Subsignal("sink_data", SimPins(8)), ), ("eth_clocks", 0, Subsignal("none", SimPins(1)), ), ("eth", 0, - Subsignal("source_stb", SimPins(1)), - Subsignal("source_ack", SimPins(1)), + Subsignal("source_valid", SimPins(1)), + Subsignal("source_ready", SimPins(1)), Subsignal("source_data", SimPins(8)), - Subsignal("sink_stb", SimPins(1)), - Subsignal("sink_ack", SimPins(1)), + Subsignal("sink_valid", SimPins(1)), + Subsignal("sink_ready", SimPins(1)), Subsignal("sink_data", SimPins(8)), ), ] diff --git a/litex/build/sim/dut_tb.cpp b/litex/build/sim/dut_tb.cpp index 0e8dac7e..f2b48046 100644 --- a/litex/build/sim/dut_tb.cpp +++ b/litex/build/sim/dut_tb.cpp @@ -19,11 +19,11 @@ /* ios */ -#ifdef SERIAL_SOURCE_STB +#ifdef SERIAL_SOURCE_VALID #define WITH_SERIAL #endif -#ifdef ETH_SOURCE_STB +#ifdef ETH_SOURCE_VALID #define WITH_ETH #endif @@ -62,7 +62,7 @@ struct sim { int eth_txbuffer_len; int eth_rxbuffer_len; int eth_rxbuffer_pos; - int eth_last_source_stb; + int eth_last_source_valid; #endif }; @@ -123,7 +123,7 @@ void eth_init(struct sim *s, const char *dev, const char*tap) s->eth_txbuffer_len = 0; s->eth_rxbuffer_len = 0; s->eth_rxbuffer_pos = 0; - s->eth_last_source_stb = 0; + s->eth_last_source_valid = 0; s->eth_dev = dev; s->eth_tap = tap; } @@ -187,8 +187,8 @@ VerilatedVcdC* tfp; int console_service(struct sim *s) { /* fpga --> console */ - SERIAL_SOURCE_ACK = 1; - if(SERIAL_SOURCE_STB == 1) { + SERIAL_SOURCE_READY = 1; + if(SERIAL_SOURCE_VALID == 1) { if(SERIAL_SOURCE_DATA == '\n') putchar('\r'); putchar(SERIAL_SOURCE_DATA); @@ -196,7 +196,7 @@ int console_service(struct sim *s) } /* console --> fpga */ - SERIAL_SINK_STB = 0; + SERIAL_SINK_VALID = 0; if(s->tick%(1000) == 0) { if(kbhit()) { char c = getch(); @@ -204,7 +204,7 @@ int console_service(struct sim *s) printf("\r\n"); return -1; } else { - SERIAL_SINK_STB = 1; + SERIAL_SINK_VALID = 1; SERIAL_SINK_DATA = c; } } @@ -263,17 +263,17 @@ int console_read(struct sim *s, unsigned char *buf) int console_service(struct sim *s) { /* fpga --> console */ - SERIAL_SOURCE_ACK = 1; - if(SERIAL_SOURCE_STB == 1) { + SERIAL_SOURCE_READY = 1; + if(SERIAL_SOURCE_VALID == 1) { s->serial_tx_data = SERIAL_SOURCE_DATA; console_write(s, &(s->serial_tx_data), 1); } /* console --> fpga */ - SERIAL_SINK_STB = 0; + SERIAL_SINK_VALID = 0; if(console_read(s, &(s->serial_rx_data))) { - SERIAL_SINK_STB = 1; + SERIAL_SINK_VALID = 1; SERIAL_SINK_DATA = s->serial_rx_data; } return 0; @@ -283,30 +283,30 @@ int console_service(struct sim *s) #ifdef WITH_ETH int ethernet_service(struct sim *s) { /* fpga --> tap */ - ETH_SOURCE_ACK = 1; - if(ETH_SOURCE_STB == 1) { + ETH_SOURCE_READY = 1; + if(ETH_SOURCE_VALID == 1) { s->eth_txbuffer[s->eth_txbuffer_len] = ETH_SOURCE_DATA; s->eth_txbuffer_len++; } else { - if(s->eth_last_source_stb) { + if(s->eth_last_source_valid) { eth_write(s, s->eth_txbuffer, s->eth_txbuffer_len); s->eth_txbuffer_len = 0; } } - s->eth_last_source_stb = ETH_SOURCE_STB; + s->eth_last_source_valid = ETH_SOURCE_VALID; /* tap --> fpga */ if(s->eth_rxbuffer_len == 0) { - ETH_SINK_STB = 0; + ETH_SINK_VALID = 0; s->eth_rxbuffer_pos = 0; s->eth_rxbuffer_len = eth_read(s, s->eth_rxbuffer); } else { if(s->eth_rxbuffer_pos < MAX(s->eth_rxbuffer_len, 60)) { - ETH_SINK_STB = 1; + ETH_SINK_VALID = 1; ETH_SINK_DATA = s->eth_rxbuffer[s->eth_rxbuffer_pos]; s->eth_rxbuffer_pos++; } else { - ETH_SINK_STB = 0; + ETH_SINK_VALID = 0; s->eth_rxbuffer_len = 0; memset(s->eth_rxbuffer, 0, 1532); } diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py index 05fc1a17..25accae6 100644 --- a/litex/build/sim/verilator.py +++ b/litex/build/sim/verilator.py @@ -31,20 +31,20 @@ def _build_tb(platform, vns, serial, template): raise ValueError try: ios += """ -#define SERIAL_SOURCE_STB dut->{serial_source_stb} -#define SERIAL_SOURCE_ACK dut->{serial_source_ack} -#define SERIAL_SOURCE_DATA dut->{serial_source_data} +#define SERIAL_SOURCE_VALID dut->{serial_source_valid} +#define SERIAL_SOURCE_READY dut->{serial_source_ready} +#define SERIAL_SOURCE_DATA dut->{serial_source_data} -#define SERIAL_SINK_STB dut->{serial_sink_stb} -#define SERIAL_SINK_ACK dut->{serial_sink_ack} -#define SERIAL_SINK_DATA dut->{serial_sink_data} +#define SERIAL_SINK_VALID dut->{serial_sink_valid} +#define SERIAL_SINK_READY dut->{serial_sink_ready} +#define SERIAL_SINK_DATA dut->{serial_sink_data} """.format( - serial_source_stb=io_name("serial", "source_stb"), - serial_source_ack=io_name("serial", "source_ack"), + serial_source_valid=io_name("serial", "source_valid"), + serial_source_ready=io_name("serial", "source_ready"), serial_source_data=io_name("serial", "source_data"), - serial_sink_stb=io_name("serial", "sink_stb"), - serial_sink_ack=io_name("serial", "sink_ack"), + serial_sink_valid=io_name("serial", "sink_valid"), + serial_sink_ready=io_name("serial", "sink_ready"), serial_sink_data=io_name("serial", "sink_data"), ) except: @@ -52,20 +52,20 @@ def _build_tb(platform, vns, serial, template): try: ios += """ -#define ETH_SOURCE_STB dut->{eth_source_stb} -#define ETH_SOURCE_ACK dut->{eth_source_ack} -#define ETH_SOURCE_DATA dut->{eth_source_data} +#define ETH_SOURCE_VALID dut->{eth_source_valid} +#define ETH_SOURCE_READY dut->{eth_source_ready} +#define ETH_SOURCE_DATA dut->{eth_source_data} -#define ETH_SINK_STB dut->{eth_sink_stb} -#define ETH_SINK_ACK dut->{eth_sink_ack} -#define ETH_SINK_DATA dut->{eth_sink_data} +#define ETH_SINK_VALID dut->{eth_sink_valid} +#define ETH_SINK_READY dut->{eth_sink_ready} +#define ETH_SINK_DATA dut->{eth_sink_data} """.format( - eth_source_stb=io_name("eth", "source_stb"), - eth_source_ack=io_name("eth", "source_ack"), + eth_source_valid=io_name("eth", "source_valid"), + eth_source_ready=io_name("eth", "source_ready"), eth_source_data=io_name("eth", "source_data"), - eth_sink_stb=io_name("eth", "sink_stb"), - eth_sink_ack=io_name("eth", "sink_ack"), + eth_sink_valid=io_name("eth", "sink_valid"), + eth_sink_ready=io_name("eth", "sink_ready"), eth_sink_data=io_name("eth", "sink_data"), ) except: diff --git a/litex/soc/cores/uart/core.py b/litex/soc/cores/uart/core.py index e902dbb7..b295b562 100644 --- a/litex/soc/cores/uart/core.py +++ b/litex/soc/cores/uart/core.py @@ -117,13 +117,13 @@ class RS232PHYModel(Module): self.source = stream.Endpoint([("data", 8)]) self.comb += [ - pads.source_stb.eq(self.sink.valid), + pads.source_valid.eq(self.sink.valid), pads.source_data.eq(self.sink.data), - self.sink.ready.eq(pads.source_ack), + self.sink.ready.eq(pads.source_ready), - self.source.valid.eq(pads.sink_stb), + self.source.valid.eq(pads.sink_valid), self.source.data.eq(pads.sink_data), - pads.sink_ack.eq(self.source.ready) + pads.sink_ready.eq(self.source.ready) ] -- 2.30.2