From 9fbd3a4ad494e0db2465710268cc162d3c66753c Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Thu, 15 Apr 2021 19:05:51 +0200 Subject: [PATCH] fix radix testcase --- src/soc/decoder/isa/test_caller_radix.py | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/soc/decoder/isa/test_caller_radix.py b/src/soc/decoder/isa/test_caller_radix.py index 338a894b..92f59170 100644 --- a/src/soc/decoder/isa/test_caller_radix.py +++ b/src/soc/decoder/isa/test_caller_radix.py @@ -14,6 +14,9 @@ from soc.decoder.isa.test_caller import run_tst testmem = { + 0x1000: # data to be read + 0x1337, + 0x10000: # PARTITION_TABLE_2 (not implemented yet) # PATB_GR=1 PRTB=0x1000 PRTS=0xb 0x800000000100000b, @@ -46,8 +49,12 @@ class DecoderTestCase(FHDLTestCase): initial_regs[1] = 0x1000 initial_regs[2] = 0x1234 sim = self.run_tst_program(program,initial_regs=initial_regs) - print(sim.gpr(1)) - self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64)) + #dump registers into file + #f = open("/tmp/debug.txt","w") + #for i in range(1,12): + # l = "r"+str(i)+" = "+str(sim.gpr(i))+"\n" + # f.write(l) + self.assertEqual(sim.gpr(3), SelectableInt(0x1337, 64)) def run_tst_program(self, prog, initial_regs=[0] * 32): # set up dummy minimal ISACaller -- 2.30.2