From 9feabfa58c7590c5a7fe698f7e0a6bb1e313355f Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Thu, 7 Jan 2021 19:02:40 +0000
Subject: [PATCH]

---
 openpower/sv/svp64.mdwn | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 2ab0967f3..9f3582b1b 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -337,6 +337,8 @@ Twin predication has an identical 3 bit field similarly encoded.
 | 110   | R30      | `R30 & (1 << i)` is non-zero |
 | 111   | ~R30     | `R30 & (1 << i)` is zero     |
 
+r10 and r30 are at the high end of temporary and unused registers, so as not to interfere with register allocation from ABIs.
+
 ## CR-based Predication (MASKMODE=1)
 
 When the predicate mode bit is one the 3 bits are interpreted as below.
-- 
2.30.2