From 9ff2e58bf1d139584ca71483aa036f7399df3882 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Sat, 16 Jan 2021 18:31:48 +0100 Subject: [PATCH] clean up test case for tlbie and dcbz --- src/soc/fu/mmu/fsm.py | 15 +++++++-------- src/soc/fu/mmu/test/test_issuer_mmu_data_path.py | 6 ++++-- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index 5cce2dde..b7967bb7 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -86,10 +86,10 @@ class FSMMMUStage(ControlBase): self.pspec.dcache = self.dcache # debugging output for gtkw - self.debug0 = Signal(64) - self.debug1 = Signal(64) - self.debug2 = Signal(64) - self.debug3 = Signal(64) + self.debug0 = Signal(4) + #self.debug1 = Signal(64) + #self.debug2 = Signal(64) + #self.debug3 = Signal(64) # for SPR field number access i = self.p.data_i @@ -150,10 +150,6 @@ class FSMMMUStage(ControlBase): # responds ("done"). with m.Switch(op.insn_type): with m.Case(MicrOp.OP_MTSPR): - comb += self.debug0.eq(0xFF) - comb += self.debug1.eq(spr) - comb += self.debug2.eq(a_i) - comb += self.debug3.eq(a_i[:32]) # subset SPR: first check a few bits with m.If(~spr[9] & ~spr[5]): with m.If(spr[0]): @@ -199,6 +195,8 @@ class FSMMMUStage(ControlBase): comb += d_in.dcbz.eq(1) # dcbz mode comb += d_in.addr.eq(a_i + b_i) # addr is (RA|0) + RB comb += done.eq(d_out.store_done) # TODO + comb += self.debug0.eq(1) + with m.Case(MicrOp.OP_TLBIE): # pass TLBIE request to MMU (spec: v3.0B p1034) @@ -211,6 +209,7 @@ class FSMMMUStage(ControlBase): comb += l_in.sprn.eq(spr) # use sprn to send insn bits comb += l_in.addr.eq(b_i) # incoming operand (RB) comb += done.eq(l_out.done) # zzzz + comb += self.debug0.eq(2) with m.If(self.n.ready_i & self.n.valid_o): m.d.sync += busy.eq(0) diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py index f2e12b99..31925c3f 100644 --- a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py +++ b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py @@ -9,12 +9,14 @@ from soc.fu.test.common import ( # this test case takes about half a minute to run on my Talos II class MMUDataPathTestCase(TestAccumulatorBase): - # MMU handles MTSPR, MFSPR, DCBZ and TLBIE. + # MMU on microwatt handles MTSPR, MFSPR, DCBZ and TLBIE. + # libre-soc has own SPR unit # other instructions here -> must be load/store def case_mfspr_after_invalid_load(self): lst = [ - "tlbie 0,0,0,0,0" # RB,RS,RIC,PRS,R + "tlbie 0,0,0,0,0", # RB,RS,RIC,PRS,R + "dcbz 1,2" ] initial_regs = [0] * 32 -- 2.30.2