From 9ff95a317ae379ec9aea16e4637a2fedc44f266c Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Sun, 25 Aug 2019 19:31:34 +0200 Subject: [PATCH] forgot to add one signal --- src/TLB/ariane/ptw.py | 1 + src/TLB/ariane/test/test_tlb.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/TLB/ariane/ptw.py b/src/TLB/ariane/ptw.py index 706d6518..ce8c774f 100644 --- a/src/TLB/ariane/ptw.py +++ b/src/TLB/ariane/ptw.py @@ -451,6 +451,7 @@ class PTW(Elaboratable): l1err = Signal(reset_less=True) l2err = Signal(reset_less=True) + l3err = Signal(reset_less=True) m.d.comb += [l3err.eq((ptw_lvl3) & pte.ppn[0:9] != Const(0,0)), l2err.eq((ptw_lvl2) & pte.ppn[0:18] != Const(0, 18)), l1err.eq((ptw_lvl1) & pte.ppn[0:27] != Const(0, 27))] diff --git a/src/TLB/ariane/test/test_tlb.py b/src/TLB/ariane/test/test_tlb.py index e10325f8..b94438ff 100644 --- a/src/TLB/ariane/test/test_tlb.py +++ b/src/TLB/ariane/test/test_tlb.py @@ -67,3 +67,4 @@ def tbench(dut): if __name__ == "__main__": dut = TLB() run_simulation(dut, tbench(dut), vcd_name="test_tlb.vcd") + print("TLB Unit Test Success") -- 2.30.2