From a0052b43df0377daae3f0b179b642b5fe825eaea Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Oct 2018 11:49:12 +0100
Subject: [PATCH] add redirection sv unit test

---
 isa/rv64ui/Makefrag.sv        |  1 +
 isa/rv64ui/sv_addi.S          |  2 ++
 isa/rv64ui/sv_addi_redirect.S | 58 +++++++++++++++++++++++++++++++++++
 3 files changed, 61 insertions(+)
 create mode 100644 isa/rv64ui/sv_addi_redirect.S

diff --git a/isa/rv64ui/Makefrag.sv b/isa/rv64ui/Makefrag.sv
index 1ad8fe1..8c9b0a6 100644
--- a/isa/rv64ui/Makefrag.sv
+++ b/isa/rv64ui/Makefrag.sv
@@ -4,6 +4,7 @@
 
 rv64ui_sv_tests = \
 	sv_addi \
+	sv_addi_redirect \
 
 rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sv_tests))
 rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sv_tests))
diff --git a/isa/rv64ui/sv_addi.S b/isa/rv64ui/sv_addi.S
index a78bcdc..e86a3f3 100644
--- a/isa/rv64ui/sv_addi.S
+++ b/isa/rv64ui/sv_addi.S
@@ -4,6 +4,8 @@
 RVTEST_RV64U        # Define TVM used by program.
 
 
+# SV test: sets up x3 and x4 with data, sets VL to 2, and carries out
+# an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
 
 # Test code region.
 RVTEST_CODE_BEGIN   # Start of test code.
diff --git a/isa/rv64ui/sv_addi_redirect.S b/isa/rv64ui/sv_addi_redirect.S
new file mode 100644
index 0000000..980cb5b
--- /dev/null
+++ b/isa/rv64ui/sv_addi_redirect.S
@@ -0,0 +1,58 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV64U        # Define TVM used by program.
+
+# SV test: sets up x3 and x4 with data, then sets up SV redirection
+# from register x16 to register x3 with a VL of 2.  the add is carried out
+# on x16 and the redirection means "actually, we want to do that add on x3"
+# and the VL means "actually we want to do that add on x3 *AND* x4"
+# x2 and x5 are tested to make sure they're not modified
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+
+        SV_LD_DATA( x2, testdata   , 0)
+        SV_LD_DATA( x3, testdata+8 , 0)
+        SV_LD_DATA( x4, testdata+16, 0)
+        SV_LD_DATA( x5, testdata+24, 0)
+
+        SET_SV_MVL(2)
+        SET_SV_CSR(1, 16, 0, 3, 1, 0)
+        SET_SV_VL(2)
+
+        addi    x16, x16, 1
+
+        CLR_SV_CSRS()
+        SET_SV_VL(0)
+        SET_SV_MVL(0)
+
+        TEST_SV_IMM(x2, 1001) # should not be modified
+        TEST_SV_IMM(x3, 42)
+        TEST_SV_IMM(x4, 43)
+        TEST_SV_IMM(x5, 1002) # should not be modified
+
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata:
+        .dword 1001
+        .dword 41
+        .dword 42
+        .dword 1002
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+
-- 
2.30.2