From a01c14cf21156416b7a4f607d7d557b5e8f26a50 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 6 Jul 2022 16:33:51 +0100 Subject: [PATCH] --- openpower/sv/cr_int_predication.mdwn | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index d6786c80f..254796f56 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -231,15 +231,15 @@ individual bits in BF may be set to 1 by ensuring that the required bit of n1 = fmsk[1] & (fmap[1] == creg[1]) n2 = fmsk[2] & (fmap[2] == creg[2]) n3 = fmsk[3] & (fmap[3] == creg[3]) - BF = BT[2:4] # select CR - bit = BT[0:1] # select bit of CR + bf = BT[2:4] # select CR field + bit = BT[0:1] # select bit of CR field n = (n0||n1||n2||n3) & fmsk result = (n != 0) if M else (n == fmsk) - CR{BF}[bit] = result + CR{bf}[bit] = result When used with SVP64 Prefixing this is a [[sv/cr_ops]] SVP64 type operation that has 5-bit Data-dependent and 5-bit Predicate-result -capability (BFT is 5 bits) +capability (BT is 5 bits) **Example Pseudo-ops:** -- 2.30.2