From a01d796de4096331a6950699d4ac66a3f3b91ef3 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Timur=20Krist=C3=B3f?= Date: Sat, 21 Sep 2019 17:58:08 +0200 Subject: [PATCH] aco: Set +wavefrontsize64 for LLVM disassembler in GFX10 wave64 mode. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Timur Kristóf Reviewed-by: Daniel Schürmann --- .../compiler/aco_instruction_selection_setup.cpp | 1 + src/amd/compiler/aco_interface.cpp | 2 +- src/amd/compiler/aco_ir.h | 5 +++-- src/amd/compiler/aco_print_asm.cpp | 14 ++++++++++---- 4 files changed, 15 insertions(+), 7 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index 7505707d4bb..06c697ccdc4 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -1241,6 +1241,7 @@ setup_isel_context(Program* program, program->info = info; program->chip_class = options->chip_class; program->family = options->family; + program->wave_size = options->wave_size; program->sgpr_limit = options->chip_class >= GFX8 ? 102 : 104; if (options->family == CHIP_TONGA || options->family == CHIP_ICELAND) program->sgpr_limit = 94; /* workaround hardware bug */ diff --git a/src/amd/compiler/aco_interface.cpp b/src/amd/compiler/aco_interface.cpp index 79dd33385dc..ad18101eb8e 100644 --- a/src/amd/compiler/aco_interface.cpp +++ b/src/amd/compiler/aco_interface.cpp @@ -147,7 +147,7 @@ void aco_compile_shader(unsigned shader_count, std::string disasm; if (get_disasm) { std::ostringstream stream; - aco::print_asm(program.get(), code, exec_size / 4u, options->family, stream); + aco::print_asm(program.get(), code, exec_size / 4u, stream); stream << '\0'; disasm = stream.str(); size += disasm.size(); diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index 24ff6a2b142..ac2bfebbcf0 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -1069,6 +1069,7 @@ public: struct radv_shader_info *info; enum chip_class chip_class; enum radeon_family family; + unsigned wave_size; Stage stage; /* Stage */ bool needs_exact = false; /* there exists an instruction with disable_wqm = true */ bool needs_wqm = false; /* there exists a p_wqm instruction */ @@ -1141,8 +1142,8 @@ void spill(Program* program, live& live_vars, const struct radv_nir_compiler_opt void insert_wait_states(Program* program); void insert_NOPs(Program* program); unsigned emit_program(Program* program, std::vector& code); -void print_asm(Program *program, std::vector& binary, unsigned exec_size, - enum radeon_family family, std::ostream& out); +void print_asm(Program *program, std::vector& binary, + unsigned exec_size, std::ostream& out); void validate(Program* program, FILE *output); bool validate_ra(Program* program, const struct radv_nir_compiler_options *options, FILE *output); #ifndef NDEBUG diff --git a/src/amd/compiler/aco_print_asm.cpp b/src/amd/compiler/aco_print_asm.cpp index d3f4c3cb40d..deb15a8b256 100644 --- a/src/amd/compiler/aco_print_asm.cpp +++ b/src/amd/compiler/aco_print_asm.cpp @@ -9,7 +9,7 @@ namespace aco { void print_asm(Program *program, std::vector& binary, - unsigned exec_size, enum radeon_family family, std::ostream& out) + unsigned exec_size, std::ostream& out) { std::vector referenced_blocks(program->blocks.size()); referenced_blocks[0] = true; @@ -30,9 +30,15 @@ void print_asm(Program *program, std::vector& binary, symbols.emplace_back(block.offset * 4, llvm::StringRef(block_names[block_names.size() - 1].data()), 0); } - LLVMDisasmContextRef disasm = LLVMCreateDisasmCPU("amdgcn-mesa-mesa3d", - ac_get_llvm_processor_name(family), - &symbols, 0, NULL, NULL); + const char *features = ""; + if (program->chip_class >= GFX10 && program->wave_size == 64) { + features = "+wavefrontsize64"; + } + + LLVMDisasmContextRef disasm = LLVMCreateDisasmCPUFeatures("amdgcn-mesa-mesa3d", + ac_get_llvm_processor_name(program->family), + features, + &symbols, 0, NULL, NULL); char outline[1024]; size_t pos = 0; -- 2.30.2