From a02077d547d603d3cbf9bcbcd365efcf084969e3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 18 May 2020 17:28:41 +0200 Subject: [PATCH] cpu/microwatt/add_sources: add use_ghdl_yosys_synth parameter to convert microwatt to verilog using GHDL-Yosys-plugin and use converted verilog for build. --- litex/soc/cores/cpu/microwatt/core.py | 29 ++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index 81802f34..513ae708 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -39,6 +39,7 @@ class Microwatt(CPU): flags += "-mno-altivec " flags += "-mlittle-endian " flags += "-mstrict-align " + flags += "-fno-stack-protector " flags += "-D__microwatt__ " return flags @@ -101,9 +102,8 @@ class Microwatt(CPU): assert reset_address == 0x00000000 @staticmethod - def add_sources(platform): - sdir = get_data_mod("cpu", "microwatt").data_location - platform.add_sources(sdir, + def add_sources(platform, use_ghdl_yosys_plugin=False): + sources = [ # Common / Types / Helpers "decode_types.vhdl", "wishbone_types.vhdl", @@ -154,8 +154,27 @@ class Microwatt(CPU): # Core "core_debug.vhdl", "core.vhdl", - ) - platform.add_source(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl")) + ] + sdir = get_data_mod("cpu", "microwatt").data_location + cdir = os.path.dirname(__file__) + if use_ghdl_yosys_plugin: + from litex.build import tools + import subprocess + ys = [] + ys.append("ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \\") + for source in sources: + ys.append(os.path.join(sdir, source) + " \\") + ys.append(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl") + " \\") + ys.append("-e microwatt_wrapper") + ys.append("chformal -assert -remove") + ys.append("write_verilog {}".format(os.path.join(cdir, "microwatt.v"))) + tools.write_to_file(os.path.join(cdir, "microwatt.ys"), "\n".join(ys)) + if subprocess.call(["yosys", "-q", "-m", "ghdl", os.path.join(cdir, "microwatt.ys")]): + raise OSError("Unable to convert Microwatt CPU to verilog, please check your GHDL-Yosys-plugin install") + platform.add_source(os.path.join(cdir, "microwatt.v")) + else: + platform.add_sources(sdir, *sources) + platform.add_source(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl")) def do_finalize(self): self.specials += Instance("microwatt_wrapper", **self.cpu_params) -- 2.30.2