From a030d6bc4354b82192a6764d499389e30e0fb61f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 7 Jul 2019 16:53:56 +0100 Subject: [PATCH] add names to flags --- src/ieee754/div_rem_sqrt_rsqrt/core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py index afc331de..245cd1c6 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py @@ -358,8 +358,8 @@ class DivPipeCoreCalculateStage(Elaboratable): l = [] for i in range(radix): next_flag = pass_flags[i + 1] if i + 1 < radix else 0 - flag = Signal(reset_less=True) - test = Signal(reset_less=True) + flag = Signal(reset_less=True, name=f"flag{i}") + test = Signal(reset_less=True, name=f"test{i}") # XXX TODO: check the width on this m.d.comb += test.eq((pass_flags[i] & ~next_flag)) m.d.comb += flag.eq(Mux(test, trial_compare_rhs_values[i], 0)) -- 2.30.2