From a03f1b22cb818671a82fad00121360eda6ce6e38 Mon Sep 17 00:00:00 2001 From: Ulrich Weigand Date: Mon, 21 Jul 2008 17:15:22 +0000 Subject: [PATCH] spu.md ("div3"): Convert into expander, move original insn and splitter contents into ... * config/spu/spu.md ("div3"): Convert into expander, move original insn and splitter contents into ... ("*div3_fast"): ... this new pattern. Enable only if flag_unsafe_math_optimizations. Add dummy scratch register. ("*div3_adjusted"): New insn and splitter. Enable only if !flag_unsafe_math_optimizations. Returns number with next highest magnitude if this is still less or equal to the true quotient in magnitude. From-SVN: r138036 --- gcc/ChangeLog | 11 ++++++++ gcc/config/spu/spu.md | 65 ++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 72 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 02675347322..4838ebe83be 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2008-07-21 Ulrich Weigand + + * config/spu/spu.md ("div3"): Convert into expander, move + original insn and splitter contents into ... + ("*div3_fast"): ... this new pattern. Enable only if + flag_unsafe_math_optimizations. Add dummy scratch register. + ("*div3_adjusted"): New insn and splitter. Enable only if + !flag_unsafe_math_optimizations. Returns number with next + highest magnitude if this is still less or equal to the true + quotient in magnitude. + 2008-07-21 Rafael Avila de Espindola * Makefile.in: Replace toplev.h with TOPLEV_H. diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md index 6985a683697..c267efd29d1 100644 --- a/gcc/config/spu/spu.md +++ b/gcc/config/spu/spu.md @@ -1721,20 +1721,33 @@ [(set_attr "type" "multi0") (set_attr "length" "80")]) -(define_insn_and_split "div3" +(define_expand "div3" + [(parallel + [(set (match_operand:VSF 0 "spu_reg_operand" "") + (div:VSF (match_operand:VSF 1 "spu_reg_operand" "") + (match_operand:VSF 2 "spu_reg_operand" ""))) + (clobber (match_scratch:VSF 3 "")) + (clobber (match_scratch:VSF 4 "")) + (clobber (match_scratch:VSF 5 ""))])] + "" + "") + +(define_insn_and_split "*div3_fast" [(set (match_operand:VSF 0 "spu_reg_operand" "=r") (div:VSF (match_operand:VSF 1 "spu_reg_operand" "r") (match_operand:VSF 2 "spu_reg_operand" "r"))) (clobber (match_scratch:VSF 3 "=&r")) - (clobber (match_scratch:VSF 4 "=&r"))] - "" + (clobber (match_scratch:VSF 4 "=&r")) + (clobber (scratch:VSF))] + "flag_unsafe_math_optimizations" "#" "reload_completed" [(set (match_dup:VSF 0) (div:VSF (match_dup:VSF 1) (match_dup:VSF 2))) (clobber (match_dup:VSF 3)) - (clobber (match_dup:VSF 4))] + (clobber (match_dup:VSF 4)) + (clobber (scratch:VSF))] { emit_insn (gen_frest_(operands[3], operands[2])); emit_insn (gen_fi_(operands[3], operands[2], operands[3])); @@ -1744,6 +1757,50 @@ DONE; }) +(define_insn_and_split "*div3_adjusted" + [(set (match_operand:VSF 0 "spu_reg_operand" "=r") + (div:VSF (match_operand:VSF 1 "spu_reg_operand" "r") + (match_operand:VSF 2 "spu_reg_operand" "r"))) + (clobber (match_scratch:VSF 3 "=&r")) + (clobber (match_scratch:VSF 4 "=&r")) + (clobber (match_scratch:VSF 5 "=&r"))] + "!flag_unsafe_math_optimizations" + "#" + "reload_completed" + [(set (match_dup:VSF 0) + (div:VSF (match_dup:VSF 1) + (match_dup:VSF 2))) + (clobber (match_dup:VSF 3)) + (clobber (match_dup:VSF 4)) + (clobber (match_dup:VSF 5))] + { + emit_insn (gen_frest_ (operands[3], operands[2])); + emit_insn (gen_fi_ (operands[3], operands[2], operands[3])); + emit_insn (gen_mul3 (operands[4], operands[1], operands[3])); + emit_insn (gen_fnms_ (operands[5], operands[4], operands[2], operands[1])); + emit_insn (gen_fma_ (operands[3], operands[5], operands[3], operands[4])); + + /* Due to truncation error, the quotient result may be low by 1 ulp. + Conditionally add one if the estimate is too small in magnitude. */ + + emit_move_insn (gen_lowpart (mode, operands[4]), + spu_const (mode, 0x80000000ULL)); + emit_move_insn (gen_lowpart (mode, operands[5]), + spu_const (mode, 0x3f800000ULL)); + emit_insn (gen_selb (operands[5], operands[5], operands[1], operands[4])); + + emit_insn (gen_add3 (gen_lowpart (mode, operands[4]), + gen_lowpart (mode, operands[3]), + spu_const (mode, 1))); + emit_insn (gen_fnms_ (operands[0], operands[2], operands[4], operands[1])); + emit_insn (gen_mul3 (operands[0], operands[0], operands[5])); + emit_insn (gen_cgt_ (gen_lowpart (mode, operands[0]), + gen_lowpart (mode, operands[0]), + spu_const (mode, -1))); + emit_insn (gen_selb (operands[0], operands[3], operands[4], operands[0])); + DONE; + }) + ;; Taken from STI's gcc ;; Does not correctly handle INF or NAN. (define_expand "divdf3" -- 2.30.2