From a062c7ab07998ce307630b3c8a50daa09828a2b2 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Thu, 25 Jun 2020 12:32:49 +0200 Subject: [PATCH] Add Wishbone read/write helpers --- gram/test/utils.py | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/gram/test/utils.py b/gram/test/utils.py index 38b8010..45b1c30 100644 --- a/gram/test/utils.py +++ b/gram/test/utils.py @@ -15,7 +15,7 @@ from nmigen.back import rtlil from nmigen._toolchain import require_tool -__all__ = ["FHDLTestCase", "runSimulation"] +__all__ = ["FHDLTestCase", "runSimulation", "wb_read", "wb_write"] def runSimulation(module, process, vcd_filename="anonymous.vcd", clock=1e-6): sim = Simulator(module) @@ -103,3 +103,38 @@ class FHDLTestCase(unittest.TestCase): stdout, stderr = proc.communicate(config) if proc.returncode != 0: self.fail("Formal verification failed:\n" + stdout) + +def wb_read(bus, addr, sel, timeout=32): + yield bus.cyc.eq(1) + yield bus.stb.eq(1) + yield bus.adr.eq(addr) + yield bus.sel.eq(sel) + yield + cycles = 0 + while not (yield bus.ack): + yield + if cycles >= timeout: + raise RuntimeError("Wishbone transaction timed out") + cycles += 1 + data = (yield bus.dat_r) + yield bus.cyc.eq(0) + yield bus.stb.eq(0) + return data + +def wb_write(bus, addr, data, sel, timeout=32): + yield bus.cyc.eq(1) + yield bus.stb.eq(1) + yield bus.adr.eq(addr) + yield bus.we.eq(1) + yield bus.sel.eq(sel) + yield bus.dat_w.eq(data) + yield + cycles = 0 + while not (yield bus.ack): + yield + if cycles >= timeout: + raise RuntimeError("Wishbone transaction timed out") + cycles += 1 + yield bus.cyc.eq(0) + yield bus.stb.eq(0) + yield bus.we.eq(0) -- 2.30.2