From a0823d72fcf19dd1112395c36432c1903ba9f98a Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 14 Nov 2021 15:11:39 +0000
Subject: [PATCH]

---
 docs/pinmux.mdwn | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 0f4e47891..93c252924 100644
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -13,7 +13,7 @@ out-enable) to be routed right the way from the ASIC, all
 the way to the IO PAD, where only then does a wire bond connect
 it to a single pin.
 
-<img src="https://www10.edacafe.com/book/ASIC/CH02/CH02-44.gif" />
+[[!img CH02-44.gif]]
 
 Designing an ASIC, there is no guarantee that the IO pad is
 working when manufactured. Worse, the peripheral could be
@@ -51,5 +51,6 @@ an ASIC that combines **both** JTAG Boundary Scan **and** GPIO
 Muxing, down to layout considerations using coriolis2.
 
 <img src="https://libre-soc.org/shakti/m_class/JTAG/jtag-block.jpg"
-  width=600 />
+  width=500 />
 
+[[!img gpio_block.png]]
-- 
2.30.2