From a08c426f1b4c07c8530c3c7e41f1f246d7f3b871 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jean-Fran=C3=A7ois=20Nguyen?= Date: Thu, 1 Jul 2021 15:49:17 +0200 Subject: [PATCH] examples/sdram_soc: reduce L1 sizes to 1KB to meet timing. --- examples/sdram_soc.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/sdram_soc.py b/examples/sdram_soc.py index bbe68eb..d3f5dcb 100644 --- a/examples/sdram_soc.py +++ b/examples/sdram_soc.py @@ -32,9 +32,9 @@ class SDRAMSoC(CPUSoC, Elaboratable): self.cpu = MinervaCPU( reset_address=reset_addr, - with_icache=True, icache_nlines=128, icache_nwords=4, icache_nways=1, + with_icache=True, icache_nlines=64, icache_nwords=4, icache_nways=1, icache_base=sdram_addr, icache_limit=sdram_addr + sdram_core.size, - with_dcache=True, dcache_nlines=128, dcache_nwords=4, dcache_nways=1, + with_dcache=True, dcache_nlines=64, dcache_nwords=4, dcache_nways=1, dcache_base=sdram_addr, dcache_limit=sdram_addr + sdram_core.size, with_muldiv=True, ) -- 2.30.2