From a09e72550a89e2943fb7da365412c0a3a5bfa45b Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 3 Oct 2022 20:57:27 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls002.mdwn | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/openpower/sv/rfc/ls002.mdwn b/openpower/sv/rfc/ls002.mdwn index ac7c8da87..5498a92e0 100644 --- a/openpower/sv/rfc/ls002.mdwn +++ b/openpower/sv/rfc/ls002.mdwn @@ -59,11 +59,12 @@ Notes: loading instruction. 2. There is no need for Special Registers (FP Flags) because this is an immediate loading instruction. No FPR Load Operations - alter `FPSCR` and neither does `lxvkq` + alter `FPSCR`, neither does `lxvkq`, and on that basis neither + should these instructions. 3. EXT001 Variants which also save similar Data-Load and Data-TLB lookups are mentioned for completeness but not included as part - of this RFC. Another Stakeholder may wish to consider submitting - them. + of this RFC. Another Stakeholder with a vested interest in 64-bit + Prefixed instructions may wish to consider submitting them. 4. `fishmv` as a Read-Modify-Write saves five unnecessary bits, making the difference between a VA/DX-Form and requiring an entire Major Opcode. -- 2.30.2