From a0c9ab2e8d6d75b2cf5b91f6f8da292ceda81408 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 22 Mar 2021 23:51:06 +0000
Subject: [PATCH] do not set sv_changed

---
 src/soc/decoder/isa/radixmmu.py | 2 +-
 src/soc/simple/issuer.py        | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/soc/decoder/isa/radixmmu.py b/src/soc/decoder/isa/radixmmu.py
index 80c8febd..9c9bdf20 100644
--- a/src/soc/decoder/isa/radixmmu.py
+++ b/src/soc/decoder/isa/radixmmu.py
@@ -220,7 +220,7 @@ class RADIX:
     def __init__(self, mem, caller):
         self.mem = mem
         self.caller = caller
-        if(caller):
+        if caller is not None:
             self.dsisr = self.caller.spr["DSISR"]
             self.dar   = self.caller.spr["DAR"]
             self.pidr  = self.caller.spr["PIDR"]
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 482d3640..aaed3508 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -595,14 +595,12 @@ class TestIssuerInternal(Elaboratable):
                               (cur_srcstep != vl):
                             comb += update_svstate.eq(1)
                             comb += new_svstate.srcstep.eq(next_srcstep)
-                            sync += sv_changed.eq(1)
 
                     if not pred_dst_zero:
                         if (((1<<cur_dststep) & self.dstmask) == 0) and
                               (cur_dststep != vl):
                             comb += new_svstate.dststep.eq(next_dststep)
                             comb += update_svstate.eq(1)
-                            sync += sv_changed.eq(1)
 
                     if update_svstate:
                         m.next = "DECODE_SV"
-- 
2.30.2