From a0cc54b5e2208625ea5c01baf6b20866e00a1bb0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 28 Jul 2018 10:58:15 +0100 Subject: [PATCH] correct address out_en name --- src/bsv/peripheral_gen/flexbus.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/bsv/peripheral_gen/flexbus.py b/src/bsv/peripheral_gen/flexbus.py index 3ab1f2b..6d73c89 100644 --- a/src/bsv/peripheral_gen/flexbus.py +++ b/src/bsv/peripheral_gen/flexbus.py @@ -52,7 +52,7 @@ class flexbus(PBase): ('tsiz', 'm_TSIZ'), ('ad_out', 'm_AD'), ('ad_in', 'm_din'), - ('ad_en', 'm_OE32n'), + ('ad_out_en', 'm_OE32n'), ]: ret.append(template.format(ps, ptype, n, stype)) return '\n'.join(ret) -- 2.30.2