From a0e02bc6026bbc0105f61cbc8262dec124cee49a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 13 Feb 2022 15:33:58 +0000 Subject: [PATCH] add future sim option (needs Simulated DDR PHY) --- src/ls2.py | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/ls2.py b/src/ls2.py index 711299e..362dfa5 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -166,12 +166,15 @@ if __name__ == "__main__": platform_kls = {'versa_ecp5': VersaECP5Platform, 'ulx3s': ULX3S_85F_Platform, 'arty_a7': ArtyA7_100Platform, + 'sim': None, }[fpga] toolchain = {'arty_a7': "yosys_nextpnr", 'versa_ecp5': 'Trellis', - 'ulx3s': 'Trellis' + 'ulx3s': 'Trellis', + 'sim': None, }.get(fpga, None) - platform = platform_kls(toolchain=toolchain) + if platform_kls is not None: + platform = platform_kls(toolchain=toolchain) # select a firmware file firmware = None @@ -180,12 +183,13 @@ if __name__ == "__main__": firmware = sys.argv[2] fw_addr = 0x0000_0000 - # get DDR and UART resource pins - ddr_pins = platform.request("ddr3", 0, - dir={"dq":"-", "dqs":"-"}, - xdr={"clk":4, "a":4, "ba":4, "clk_en":4, - "odt":4, "ras":4, "cas":4, "we":4}) - uart_pins = platform.request("uart", 0) + if platform is not None: + # get DDR and UART resource pins + ddr_pins = platform.request("ddr3", 0, + dir={"dq":"-", "dqs":"-"}, + xdr={"clk":4, "a":4, "ba":4, "clk_en":4, + "odt":4, "ras":4, "cas":4, "we":4}) + uart_pins = platform.request("uart", 0) # set up the SOC soc = DDR3SoC(ddrphy_addr=0xff000000, # DRAM firmware init base -- 2.30.2