From a0ff23dde21444526d34a0198cc5c6aa82af7883 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 21 Sep 2019 10:54:12 +0100 Subject: [PATCH] --- nlnet_2019_video.mdwn | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/nlnet_2019_video.mdwn b/nlnet_2019_video.mdwn index ecf3a3ce5..254fb464e 100644 --- a/nlnet_2019_video.mdwn +++ b/nlnet_2019_video.mdwn @@ -51,6 +51,7 @@ The tasks, which will need to be iteratively applied, are as follows: * to implement those instructions in actual hardware, for running in an FPGA * to follow through with the upstream submission and acceptance of customisation of relevant software libre video decode projects and toolchains. +This needs to be done iteratively because it is only when a certain high level of functionality is reached (FPGA, full simulation) will it be possible to properly determine if the proposed instructions actually meet the requirements. # Does the project have other funding sources, both past and present? @@ -58,14 +59,7 @@ The overall project has sponsorship from Purism as well as a prior grant from NLNet. However that is for specifically covering the development of the RTL (the hardware source code). -There is no source of funds for the work on the *next* stage: the actual -VLSI ASIC Layout. Chips4Makers is however putting in an *additional* -(and separate) funding application for the stage after *this*: the -creation of the Cell Libraries that will be used in the VLSI ASIC Layout. - -All these three projects are separate and distinct (despite being related -to the same CPU), and funding may not cross over from one project to -the other. +There is no source of funds for the work on the # Compare your own project with existing or historical efforts. -- 2.30.2