From a12bb615e5d65263eea43153c09c72f537b40514 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 15 Dec 2020 18:37:27 -0800 Subject: [PATCH] change to more well-known vector op names --- openpower/sv/svp_rewrite/svp64.mdwn | 10 +++++----- openpower/sv/svp_rewrite/svp64/discussion.mdwn | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index a9a2fa4d8..0bba84923 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -147,10 +147,10 @@ CR based predication. TODO: select alternate CR for twin predication? see [[dis This is a novel concept that allows predication to be applied to a single source and a single dest register. The following types of traditional Vector operations may be encoded with it, *without requiring explicit opcodes to do so* * VSPLAT (a single scalar distributed across a vector) -* VEXTRACT (a single scalar taken from a vector) -* VINSERT (a scalar inserted into a vector) -* VREDUCE (sequential selection of certain elements) -* VEXPAND (insertion of a sequence of elements) +* VEXTRACT (like LLVM IR [`extractelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#extractelement-instruction)) +* VINSERT (like LLVM IR [`insertelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#insertelement-instruction)) +* VCOMPRESS (like LLVM IR [`llvm.masked.compressstore.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-compressstore-intrinsics)) +* VEXPAND (like LLVM IR [`llvm.masked.expandload.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-expandload-intrinsics)) Those patterns (and more) may be applied to: @@ -163,7 +163,7 @@ Those patterns (and more) may be applied to: This is a huge list that creates extremely powerful combinations, particularly given that one of the predicate options is `(1<