From a13a706a207296b40dbe43576fad423cf5f4679a Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 1 Aug 2009 22:50:14 -0700 Subject: [PATCH] Fix setting of INST_FETCH flag for O3 CPU. It's still broken in inorder. Also enhance DPRINTFs in cache and physical memory so we can see more easily whether it's getting set or not. --- src/cpu/base_dyn_inst.hh | 10 ++++------ src/cpu/o3/fetch_impl.hh | 6 +++--- src/cpu/ozone/inorder_back_end.hh | 4 ---- src/cpu/simple/base.cc | 1 - src/mem/cache/cache_impl.hh | 5 +++-- src/mem/physical.cc | 12 +++++++----- 6 files changed, 17 insertions(+), 21 deletions(-) diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index c6e57b612..f4ff88209 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -857,9 +857,8 @@ inline Fault BaseDynInst::read(Addr addr, T &data, unsigned flags) { reqMade = true; - Request *req = new Request(); - req->setVirt(asid, addr, sizeof(T), flags, this->PC); - req->setThreadContext(thread->contextId(), threadNumber); + Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, + thread->contextId(), threadNumber); fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read); @@ -913,9 +912,8 @@ BaseDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res) } reqMade = true; - Request *req = new Request(); - req->setVirt(asid, addr, sizeof(T), flags, this->PC); - req->setThreadContext(thread->contextId(), threadNumber); + Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, + thread->contextId(), threadNumber); fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index a76e07576..3781113bd 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -596,9 +596,9 @@ DefaultFetch::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID tid // Setup the memReq to do a read of the first instruction's address. // Set the appropriate read size and flags as well. // Build request here. - RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, - fetch_PC, cpu->thread[tid]->contextId(), - tid); + RequestPtr mem_req = + new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH, + fetch_PC, cpu->thread[tid]->contextId(), tid); memReq[tid] = mem_req; diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh index dd9e23f97..f242645a2 100644 --- a/src/cpu/ozone/inorder_back_end.hh +++ b/src/cpu/ozone/inorder_back_end.hh @@ -211,7 +211,6 @@ InorderBackEnd::read(Addr addr, T &data, unsigned flags) memReq->cmd = Read; memReq->completionEvent = NULL; memReq->time = curTick; - memReq->flags &= ~INST_FETCH; MemAccessResult result = dcacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is @@ -252,7 +251,6 @@ InorderBackEnd::write(T data, Addr addr, unsigned flags, uint64_t *res) // memcpy(memReq->data,(uint8_t *)&data,memReq->size); memReq->completionEvent = NULL; memReq->time = curTick; - memReq->flags &= ~INST_FETCH; MemAccessResult result = dcacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is @@ -293,7 +291,6 @@ InorderBackEnd::read(MemReqPtr &req, T &data, int load_idx) req->time = curTick; assert(!req->data); req->data = new uint8_t[64]; - req->flags &= ~INST_FETCH; Fault fault = cpu->read(req, data); memcpy(req->data, &data, sizeof(T)); @@ -363,7 +360,6 @@ InorderBackEnd::write(MemReqPtr &req, T &data, int store_idx) memcpy(req->data,(uint8_t *)&data,req->size); req->completionEvent = NULL; req->time = curTick; - req->flags &= ~INST_FETCH; MemAccessResult result = dcacheInterface->access(req); // Ugly hack to get an event scheduled *only* if the access is diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 921c8c19d..732bb637b 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -282,7 +282,6 @@ BaseSimpleCPU::copy(Addr dest) memReq->dest = dest_addr; memReq->size = 64; memReq->time = curTick; - memReq->flags &= ~INST_FETCH; dcacheInterface->access(memReq); } } diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 0940893bc..80b7c545c 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -268,8 +268,9 @@ Cache::access(PacketPtr pkt, BlkType *&blk, blk = tags->accessBlock(pkt->getAddr(), lat); - DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(), pkt->getAddr(), - (blk) ? "hit" : "miss"); + DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(), + pkt->req->isInstFetch() ? " (ifetch)" : "", + pkt->getAddr(), (blk) ? "hit" : "miss"); if (blk != NULL) { diff --git a/src/mem/physical.cc b/src/mem/physical.cc index 5680fd970..d87ad3b22 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -211,8 +211,8 @@ PhysicalMemory::checkLockedAddrList(PacketPtr pkt) #define CASE(A, T) \ case sizeof(T): \ - DPRINTF(MemoryAccess, A " of size %i on address 0x%x data 0x%x\n", \ - pkt->getSize(), pkt->getAddr(), pkt->get()); \ + DPRINTF(MemoryAccess,"%s of size %i on address 0x%x data 0x%x\n", \ + A, pkt->getSize(), pkt->getAddr(), pkt->get()); \ break @@ -224,8 +224,8 @@ PhysicalMemory::checkLockedAddrList(PacketPtr pkt) CASE(A, uint16_t); \ CASE(A, uint8_t); \ default: \ - DPRINTF(MemoryAccess, A " of size %i on address 0x%x\n", \ - pkt->getSize(), pkt->getAddr()); \ + DPRINTF(MemoryAccess, "%s of size %i on address 0x%x\n", \ + A, pkt->getSize(), pkt->getAddr()); \ } \ } while (0) @@ -281,6 +281,7 @@ PhysicalMemory::doAtomicAccess(PacketPtr pkt) if (overwrite_mem) std::memcpy(hostAddr, &overwrite_val, pkt->getSize()); + assert(!pkt->req->isInstFetch()); TRACE_PACKET("Read/Write"); } else if (pkt->isRead()) { assert(!pkt->isWrite()); @@ -289,11 +290,12 @@ PhysicalMemory::doAtomicAccess(PacketPtr pkt) } if (pmemAddr) memcpy(pkt->getPtr(), hostAddr, pkt->getSize()); - TRACE_PACKET("Read"); + TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read"); } else if (pkt->isWrite()) { if (writeOK(pkt)) { if (pmemAddr) memcpy(hostAddr, pkt->getPtr(), pkt->getSize()); + assert(!pkt->req->isInstFetch()); TRACE_PACKET("Write"); } } else if (pkt->isInvalidate()) { -- 2.30.2