From a148af97ba99e1b22f2fa51dcacee9e22efd7bd1 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 1 Apr 2015 16:49:32 +0800 Subject: [PATCH] soc: retrieve csr and memory regions using methods --- make.py | 10 ++++++---- misoclib/soc/__init__.py | 20 +++++++++++++------- 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/make.py b/make.py index 4253dc1b..f3a4ad86 100755 --- a/make.py +++ b/make.py @@ -86,6 +86,8 @@ if __name__ == "__main__": top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) soc = top_class(platform, **top_kwargs) soc.finalize() + memory_regions = soc.get_memory_regions() + csr_regions = soc.get_csr_regions() # decode actions action_list = ["clean", "build-bitstream", "build-headers", "build-csr-csv", "build-bios", @@ -151,20 +153,20 @@ CPU type: {} linker_output_format = cpuif.get_linker_output_format(soc.cpu_type) write_to_file("software/include/generated/output_format.ld", linker_output_format) - linker_regions = cpuif.get_linker_regions(soc.memory_regions) + linker_regions = cpuif.get_linker_regions(memory_regions) write_to_file("software/include/generated/regions.ld", boilerplate + linker_regions) for sdram_phy in ["sdrphy", "ddrphy"]: if hasattr(soc, sdram_phy): sdram_phy_header = initsequence.get_sdram_phy_header(getattr(soc, sdram_phy).settings) write_to_file("software/include/generated/sdram_phy.h", boilerplate + sdram_phy_header) - mem_header = cpuif.get_mem_header(soc.memory_regions, getattr(soc, "flash_boot_address", None)) + mem_header = cpuif.get_mem_header(memory_regions, getattr(soc, "flash_boot_address", None)) write_to_file("software/include/generated/mem.h", boilerplate + mem_header) - csr_header = cpuif.get_csr_header(soc.csr_regions, soc.interrupt_map) + csr_header = cpuif.get_csr_header(csr_regions, soc.interrupt_map) write_to_file("software/include/generated/csr.h", boilerplate + csr_header) if actions["build-csr-csv"]: - csr_csv = cpuif.get_csr_csv(soc.csr_regions) + csr_csv = cpuif.get_csr_csv(csr_regions) write_to_file(args.csr_csv, csr_csv) if actions["build-bios"]: diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py index e86f1a23..9bf9b5e5 100644 --- a/misoclib/soc/__init__.py +++ b/misoclib/soc/__init__.py @@ -72,8 +72,8 @@ class SoC(Module): self.csr_data_width = csr_data_width self.csr_address_width = csr_address_width - self.memory_regions = [] - self.csr_regions = [] # list of (name, origin, busword, csr_list/Memory) + self._memory_regions = [] # list of (name, origin, length) + self._csr_regions = [] # list of (name, origin, busword, csr_list/Memory) self._wb_masters = [] self._wb_slaves = [] @@ -135,11 +135,11 @@ class SoC(Module): def add_memory_region(self, name, origin, length): def in_this_region(addr): return addr >= origin and addr < origin + length - for n, o, l in self.memory_regions: + for n, o, l in self._memory_regions: if n == name or in_this_region(o) or in_this_region(o+l-1): raise ValueError("Memory region conflict between {} and {}".format(n, name)) - self.memory_regions.append((name, origin, length)) + self._memory_regions.append((name, origin, length)) def register_mem(self, name, address, interface, size=None): self.add_wb_slave(mem_decoder(address), interface) @@ -150,17 +150,23 @@ class SoC(Module): self.add_wb_slave(mem_decoder(self.mem_map["rom"]), interface) self.add_memory_region("rom", self.cpu_reset_address, rom_size) + def get_memory_regions(self): + return self._memory_regions + def check_csr_region(self, name, origin): - for n, o, l, obj in self.csr_regions: + for n, o, l, obj in self._csr_regions: if n == name or o == origin: raise ValueError("CSR region conflict between {} and {}".format(n, name)) def add_csr_region(self, name, origin, busword, obj): self.check_csr_region(name, origin) - self.csr_regions.append((name, origin, busword, obj)) + self._csr_regions.append((name, origin, busword, obj)) + + def get_csr_regions(self): + return self._csr_regions def do_finalize(self): - registered_mems = [regions[0] for regions in self.memory_regions] + registered_mems = [regions[0] for regions in self._memory_regions] if isinstance(self.cpu_or_bridge, CPU): for mem in ["rom", "sram"]: if mem not in registered_mems: -- 2.30.2