From a15a3f9cfb4fa832f12e63d9c58a088eddc16e4e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 8 Jul 2019 10:40:25 +0100 Subject: [PATCH] add simulation fns based on num_rows --- src/ieee754/fpcommon/test/fpmux.py | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py index 601e5461..273c8025 100644 --- a/src/ieee754/fpcommon/test/fpmux.py +++ b/src/ieee754/fpcommon/test/fpmux.py @@ -10,7 +10,7 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -class InputTest: +class MuxInOut: def __init__(self, dut, width, fpkls, fpop, vals, single_op): self.dut = dut self.fpkls = fpkls @@ -178,11 +178,9 @@ def runfp(dut, width, name, fpkls, fpop, single_op=False, n_vals=10, vals=None): if vals is None: vals = create_random(dut.num_rows, width, single_op, n_vals) - test = InputTest(dut, width, fpkls, fpop, vals, single_op) - run_simulation(dut, [test.rcv(1), test.rcv(0), - test.rcv(3), test.rcv(2), - test.send(0), test.send(1), - test.send(3), test.send(2), - ], - vcd_name="%s.vcd" % name) - + test = MuxInOut(dut, width, fpkls, fpop, vals, single_op) + fns = [] + for i in range(dut.num_rows): + fns.append(test.rcv(i)) + fns.append(test.send(i)) + run_simulation(dut, fns, vcd_name="%s.vcd" % name) -- 2.30.2