From a1820fc4739db8d7d5abfdd15e2e49fe1beb7ad4 Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 28 Jun 2022 10:53:23 +0100 Subject: [PATCH] --- openpower/sv/branches.mdwn | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index 5f5be19fb..59252d83f 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -103,7 +103,7 @@ has no special impact, regardless of whether the branch occurred or not. This can leave srcstep etc. in what may be considered an unusual state on exit from a loop and it is up to the programmer to -reset srcstep, dststep etc. to known-good values. +reset srcstep, dststep etc. to known-good values *(achieved with `setvl`)*. Additional useful behaviour involves two primary Modes (both of which may be enabled and combined): @@ -364,6 +364,13 @@ This avoids destruction of LR during loops (particularly Vertical-First ones). +**SVLR and SVSTATE** + +For precisely the reasons why `LK=1` was added originally to the Power +ISA, with SVSTATE being a peer of the Program Counter it becomes +necessary to also add an SVLR (SVSTATE Link Register) +and corresponding control bits `SL` and `SLu`. + ## CTR-test Where a standard Scalar v3.0B branch unconditionally decrements @@ -635,11 +642,14 @@ for srcstep in range(VL): break # loop finally done, now test if branch (and update LR) lr_ok <- LK +svlr_ok <- SVRMmode.SL if cond_ok then if AA then NIA <-iea EXTS(BD || 0b00) else NIA <-iea CIA + EXTS(BD || 0b00) if SVRMmode.LRu then lr_ok <- ¬lr_ok + if SVRMmode.SLu then svlr_ok <- ¬svlr_ok if lr_ok then LR <-iea CIA + 4 +if svlr_ok then SVLR <- SVSTATE ``` Pseudocode for Vertical-First Mode: -- 2.30.2