From a18e3393d8437ea8d0507f836f570d31c8d4380a Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Apr 2019 12:09:46 +0100
Subject: [PATCH] add new buffermode=False unit test, reorg a bit

---
 src/add/test_buf_pipe.py | 85 +++++++++++++++++++++++++++++-----------
 1 file changed, 62 insertions(+), 23 deletions(-)

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 83880cdb..327d0fc4 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -28,7 +28,7 @@ from singlepipe import UnbufferedPipeline2
 
 from random import randint, seed
 
-seed(0)
+#seed(0)
 
 
 def check_o_n_valid(dut, val):
@@ -634,25 +634,6 @@ class ExampleBufDelayedPipe(BufferedPipeline):
         return m
 
 
-class ExampleBufPipe3(ControlBase):
-    """ Example of how to do delayed pipeline, where the stage signals
-        whether it is ready.
-    """
-
-    def elaborate(self, platform):
-        m = ControlBase._elaborate(self, platform)
-
-        #pipe1 = ExampleBufDelayedPipe()
-        pipe1 = ExampleBufDelayedPipe()
-        pipe2 = ExampleBufPipe()
-
-        m.submodules.pipe1 = pipe1
-        m.submodules.pipe2 = pipe2
-
-        m.d.comb += self.connect([pipe1, pipe2])
-
-        return m
-
 def data_chain1():
         data = []
         for i in range(num_tests):
@@ -684,6 +665,55 @@ class ExampleUnBufDelayedPipe(UnbufferedPipeline):
         m.submodules.stage = self.stage
         return m
 
+######################################################################
+# Test 14
+######################################################################
+
+class ExampleBufPipe3(ControlBase):
+    """ Example of how to do delayed pipeline, where the stage signals
+        whether it is ready.
+    """
+
+    def elaborate(self, platform):
+        m = ControlBase._elaborate(self, platform)
+
+        pipe1 = ExampleBufDelayedPipe()
+        pipe2 = ExampleBufPipe()
+
+        m.submodules.pipe1 = pipe1
+        m.submodules.pipe2 = pipe2
+
+        m.d.comb += self.connect([pipe1, pipe2])
+
+        return m
+
+######################################################################
+# Test 15
+######################################################################
+
+class ExampleBufModeAdd1Pipe(BufferedPipeline):
+
+    def __init__(self):
+        stage = ExampleStageCls()
+        BufferedPipeline.__init__(self, stage, buffermode=False)
+
+
+class ExampleBufModeUnBufPipe(ControlBase):
+
+    def elaborate(self, platform):
+        m = ControlBase._elaborate(self, platform)
+
+        pipe1 = ExampleBufModeAdd1Pipe()
+        pipe2 = ExampleBufAdd1Pipe()
+
+        m.submodules.pipe1 = pipe1
+        m.submodules.pipe2 = pipe2
+
+        m.d.comb += self.connect([pipe1, pipe2])
+
+        return m
+
+
 ######################################################################
 # Test 999 - XXX FAILS
 # http://bugs.libre-riscv.org/show_bug.cgi?id=57
@@ -827,7 +857,6 @@ if __name__ == '__main__':
 
 
     print ("test 12")
-    #dut = ExampleBufPipe3()
     dut = ExampleBufDelayedPipe()
     data = data_chain1()
     test = Test5(dut, test12_resultfn, data=data)
@@ -840,7 +869,6 @@ if __name__ == '__main__':
         f.write(vl)
 
     print ("test 13")
-    #dut = ExampleBufPipe3()
     dut = ExampleUnBufDelayedPipe()
     data = data_chain1()
     test = Test5(dut, test12_resultfn, data=data)
@@ -854,7 +882,6 @@ if __name__ == '__main__':
 
     print ("test 14")
     dut = ExampleBufPipe3()
-    #dut = ExampleBufDelayedPipe()
     data = data_chain1()
     test = Test5(dut, test9_resultfn, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd")
@@ -865,6 +892,18 @@ if __name__ == '__main__':
     with open("test_bufpipe14.il", "w") as f:
         f.write(vl)
 
+    print ("test 15)")
+    dut = ExampleBufModeUnBufPipe()
+    data = data_chain1()
+    test = Test5(dut, test9_resultfn, data=data)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd")
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             [dut.p.i_data] + [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_bufunbuf999.il", "w") as f:
+        f.write(vl)
+
     print ("test 999 (expected to fail, which is a bug)")
     dut = ExampleBufUnBufPipe()
     data = data_chain1()
-- 
2.30.2