From a1ac6cdb3ac61570b729b6dd8863a6b60c5a7810 Mon Sep 17 00:00:00 2001 From: IkiWiki Date: Thu, 29 Sep 2022 23:47:13 +0100 Subject: [PATCH] dummy commit --- openpower/sv/rfc/ls001.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 86d46a816..09cdb52dc 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -156,7 +156,7 @@ strongly recommended, to avoid a Read-Modify-Write cycle. The only major concern is in the upper SV Extension Levels: the Hazard Management for increased number of Scalar Registers to 128 (in current versions) but given that IBM POWER9/10 has VSX register numbering 64, -and modern GPUs have 128, 256 amd even 512 registers this was deemed +and modern GPUs have 128, 256 and even 512 registers this was deemed acceptable. Strategies do exist in hardware for Hazard Management of such large numbers of registers, even for Multi-Issue microarchitectures. -- 2.30.2