From a1ad30faab428905349214643837a1deed861b20 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 17 Feb 2012 11:08:41 +0100 Subject: [PATCH] fhdl/verilog: properly connect instance inouts --- migen/fhdl/verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 3b6655e7..e68071ae 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -198,7 +198,7 @@ def _printinstances(f, ns, clk, rst): r += ns.get_name(x) if x.parameters: r += " " r += "(\n" - ports = list(x.ins.items()) + list(x.outs.items()) + ports = list(x.ins.items()) + list(x.outs.items()) + list(x.inouts.items()) if x.clkport: ports.append((x.clkport, clk)) if x.rstport: -- 2.30.2