From a1de471a5563c09800ca543b08dbf51d650faf44 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 11 Sep 2019 14:32:05 +0100
Subject: [PATCH]

---
 zfpacc_proposal.mdwn | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/zfpacc_proposal.mdwn b/zfpacc_proposal.mdwn
index 381645595..4f2aea2fd 100644
--- a/zfpacc_proposal.mdwn
+++ b/zfpacc_proposal.mdwn
@@ -71,17 +71,20 @@ TODO: reduced accuracy
 
 # Dynamic accuracy CSR <a name="dynamic"></a>
 
+FCSR to be modified to include accuracy bits:
+
 | 31....11 | 10..8  | 7..5 | 4....0 |
 | -------- | ------ | ---- | ------ |
 | reserved | facc   | frm  | fflags |
 
-[[!table data="""
-| facc  | mode    | description         | 
+The values for the field facc to include the following:
+
+| facc  | mode    | description         |
+| ----- | ------- | ------------------- |
 | 0b000 | IEEE754 | correctly rounded   | 
 | 0b010 | ULP<1   | Unit Last Place < 1 | 
 | 0b100 | Vulkan  | Vulkan compliant    | 
-| 0b110 | Appx    | Machine Learning    | 
-"""]]
+| 0b110 | Appx    | Machine Learning    |
 
 maybe a solution would be to add an extra field to the fp control csr
 to allow selecting one of several accurate or fast modes:
-- 
2.30.2