From a1e6556659b33fcd1f8beec2fd7d0e32c682cbc4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 7 Sep 2020 17:22:52 +0100 Subject: [PATCH] convert mul test to use Power Decode subset --- src/soc/decoder/isa/caller.py | 7 ++++--- src/soc/fu/mul/test/test_pipe_caller.py | 8 +++++--- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index b4c7f1fe..3c7689f0 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -462,9 +462,10 @@ class ISACaller: self.spr['XER'][XER_bits['CA32']] = cy32 def handle_overflow(self, inputs, outputs, div_overflow): - inv_a = yield self.dec2.e.do.invert_in - if inv_a: - inputs[0] = ~inputs[0] + if hasattr(self.dec2.e.do, "invert_in"): + inv_a = yield self.dec2.e.do.invert_in + if inv_a: + inputs[0] = ~inputs[0] imm_ok = yield self.dec2.e.do.imm_data.ok if imm_ok: diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py index d45f1978..1c2ad912 100644 --- a/src/soc/fu/mul/test/test_pipe_caller.py +++ b/src/soc/fu/mul/test/test_pipe_caller.py @@ -189,9 +189,11 @@ class TestRunner(unittest.TestCase): comb = m.d.comb instruction = Signal(32) - pdecode = create_pdecode() + fn_name = "MUL" + opkls = MulPipeSpec.opsubsetkls - m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) + m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name) + pdecode = pdecode2.dec pspec = MulPipeSpec(id_wid=2) m.submodules.alu = alu = MulBasePipe(pspec) @@ -261,7 +263,7 @@ class TestRunner(unittest.TestCase): def check_alu_outputs(self, alu, dec2, sim, code): - rc = yield dec2.e.do.rc.data + rc = yield dec2.e.do.rc.rc cridx_ok = yield dec2.e.write_cr.ok cridx = yield dec2.e.write_cr.data -- 2.30.2