From a20c6cbe15985e3a4716b2e4b25e1c999133ea3e Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 13 May 2022 20:13:04 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index ee1148c2c..90e858952 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -378,8 +378,8 @@ Integer and Floating-point Scalar register files were dropped approximately a decade ago after the Packed SIMD variants were considered to be duplicates. With it being completely inappropriate to attempt to Vectorise a Packed SIMD ISA designed 20 years ago with no Predication of any kind, -the Scalar ISA, a much better all-round candidate for Vectorisation is -left anaemic. +the Scalar ISA, a much better all-round candidate for Vectorisation +(the Scalar parts of Power ISA) is left anaemic. A particular key instruction that is missing is `MV.X` which is illustrated as `GPR(dest) = GPR(GPR(src))`. This horrendously -- 2.30.2