From a2351e43cf925dd37aaf033f57228d58e3dd7227 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 26 May 2022 18:00:33 +0100 Subject: [PATCH] add preamble on reg field encoding --- src/openpower/sv/trans/svp64.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 05059e48..d74004cb 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -562,6 +562,14 @@ class SVP64Asm: # XXX also TODO: the LD/ST modes which are different # https://libre-soc.org/openpower/sv/ldst/ + # rright. SVP64 register numbering is from 0 to 127 + # for GPRs, FPRs *and* CR Fields, where for v3.0 the GPRs and RPFs + # are 0-31 and CR Fields are only 0-7. the SVP64 RM "Extra" + # area is used to extend the numbering from the 32-bit + # instruction, and also to record whether the register + # is scalar or vector. on a per-operand basis. this + # results in a slightly finnicky encoding: here we go... + # encode SV-GPR and SV-FPR field into extra, v3.0field if rtype in ['GPR', 'FPR']: sv_extra, field = get_extra_gpr(etype, regmode, field) -- 2.30.2