From a23d9409e7d04fcfa31a139d0cf6169be4c46fca Mon Sep 17 00:00:00 2001
From: =?utf8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 22 May 2021 20:27:51 +0200
Subject: [PATCH] opt_mem: Remove write ports with const-0 EN.

Fixes #2765.
---
 passes/opt/opt_mem.cc | 12 ++++++++++++
 tests/opt/bug2765.ys  | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 46 insertions(+)
 create mode 100644 tests/opt/bug2765.ys

diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc
index 49a0ac51a..0409fb736 100644
--- a/passes/opt/opt_mem.cc
+++ b/passes/opt/opt_mem.cc
@@ -52,6 +52,18 @@ struct OptMemPass : public Pass {
 		int total_count = 0;
 		for (auto module : design->selected_modules()) {
 			for (auto &mem : Mem::get_selected_memories(module)) {
+				bool changed = false;
+				for (auto &port : mem.wr_ports) {
+					if (port.en.is_fully_zero()) {
+						port.removed = true;
+						changed = true;
+						total_count++;
+					}
+				}
+				if (changed) {
+					mem.emit();
+				}
+
 				if (mem.wr_ports.empty() && mem.inits.empty()) {
 					mem.remove();
 					total_count++;
diff --git a/tests/opt/bug2765.ys b/tests/opt/bug2765.ys
new file mode 100644
index 000000000..de670c2d1
--- /dev/null
+++ b/tests/opt/bug2765.ys
@@ -0,0 +1,34 @@
+read_verilog << EOT
+
+module top(...);
+
+input clk;
+input [3:0] wa;
+input [15:0] wd;
+input [3:0] ra;
+output [15:0] rd;
+
+reg [15:0] mem[0:15];
+
+integer i;
+reg x;
+
+always @(posedge clk) begin
+        for (i = 0; i < 2; i = i + 1) begin
+                x = i == 1;
+                if (x)
+                        mem[wa] <= wd;
+        end
+end
+
+assign rd = mem[ra];
+
+endmodule
+
+EOT
+
+proc
+opt
+select -assert-count 2 t:$memwr
+opt_mem
+select -assert-count 1 t:$memwr
-- 
2.30.2