From a26ac8e502fc8d39a21366103017ed2e98982013 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 11 Jun 2020 11:53:21 +0100 Subject: [PATCH] fixing get_rd_sim_xer_ca, has to only read carry if available --- src/soc/fu/compunits/test/test_alu_compunit.py | 2 +- src/soc/fu/test/common.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py index 514bb0bb..9ad8a46c 100644 --- a/src/soc/fu/compunits/test/test_alu_compunit.py +++ b/src/soc/fu/compunits/test/test_alu_compunit.py @@ -40,7 +40,7 @@ class ALUTestRunner(TestRunner): yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2) ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py index b6ba048f..e61edb48 100644 --- a/src/soc/fu/test/common.py +++ b/src/soc/fu/test/common.py @@ -3,7 +3,7 @@ Bugreports: * https://bugs.libre-soc.org/show_bug.cgi?id=361 """ -from soc.decoder.power_enums import XER_bits +from soc.decoder.power_enums import XER_bits, CryIn from soc.regfile.util import fast_reg_to_spr # HACK! @@ -71,7 +71,7 @@ class ALUHelpers: def get_rd_sim_xer_ca(res, sim, dec2): cry_in = yield dec2.e.input_carry - if cry_in: + if cry_in == CryIn.CA.value: expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0 expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0 res['xer_ca'] = expected_carry | (expected_carry32 << 1) -- 2.30.2