From a2d57c70c0481fe8fb809d2ae44ce779150c2226 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 9 Oct 2022 21:02:02 +0100
Subject: [PATCH]

---
 openpower/sv/rfc/ls002/discussion.mdwn | 28 +++++++++++++++++++++-----
 1 file changed, 23 insertions(+), 5 deletions(-)

diff --git a/openpower/sv/rfc/ls002/discussion.mdwn b/openpower/sv/rfc/ls002/discussion.mdwn
index 28e512ff2..4f9a9b380 100644
--- a/openpower/sv/rfc/ls002/discussion.mdwn
+++ b/openpower/sv/rfc/ls002/discussion.mdwn
@@ -41,6 +41,7 @@ be a different matter.
    "Move" for instructions that transfer data between registers.  Here are
    two approaches.
 **
+
 ```
    a. Model the instructions on li (Load Immediate), an extended mnemonic for
       addi.
@@ -63,7 +64,7 @@ be a different matter.
 
 the fact that they bypass D-Cache and correspondingly raise no flags or
 exceptions is the connection to `ld`.  despite that i like (a) as well
-although for purely non-technical reasons, more "memorable", i do love
+although for purely non-technical reasons (more "memorable") i do love
 the two mnemonics `flis fishmv` :)
 
 we picked "s" on the end of `fmvis` (`flis`) because it is "shifted"
@@ -78,14 +79,14 @@ Other:
   which in V. 3.1B are E, F, G, and H.
 **
 
-ackniwledged.  will edit
+acknowledged.  will edit. done.
 
 **
 2. Additional affected sections are 1.6.1.6 (additional line for DX-form),
    1.6.2 (additional use for d0,d1,d2), and Appendix D (Opcode Maps).
 **
 
-ditto
+ditto. TODO.
 
 **
 3. Does the last line of the Summary apply to both instructions or just to
@@ -104,10 +105,11 @@ the cost of doing so is:
 * 1x64 pfishmv
 
 which is QTY 8 bytes which is actually *more* than just `fld`,
-which is only QTY 6 bytes.  the only technical reason therefore
+which is only QTY 6 bytes.  the only technical reason therefore is
 to avoid D-Cache entirely, just like the 5-instruction sequence
 that writes a 64-bit GPR only from immediates
-(li, oris, rldicl, li, oris)
+(li, oris, rldicl, li, oris) although that is justifiable
+as a critical means of bootstrapping (constructing 64 bit addresses)
 
 **
 4. The Motivation says "Even clearing an FPR to zero presently requires Load".
@@ -126,6 +128,8 @@ didn't know about it! although technically that reads registers
 6. The RTL for fmvis should use left arrow for assignment.
 **
 
+RTL error corrected. ack on FRT.
+
 **
 7. The architecture spec (VSX chapter) uses "BFP32" and "BFP64", and the
    lower-case versions thereof, for the 32-bit and 64-bit binary FP formats.
@@ -133,12 +137,16 @@ didn't know about it! although technically that reads registers
    consistent with this usage.
 **
 
+acknowledged. TODO.
+
 **
 8. More generally, the style of the verbal description for both instructions
    should be made more consistent with the style used in the architecture
    spec.
 **
 
+yes Paul kindly gave advice on that.
+
 **
 9. In the first clause of the verbal description of fishmv I think "inserted
    into FRS" should be "inserted into the low-order half of the single-
@@ -147,6 +155,8 @@ didn't know about it! although technically that reads registers
    paragraph.
 **
 
+ack. TODO.
+
 **
 10. The paragraph before the Programming Note in the fishmv description
    says "This is strategically similar to how li combined with oris is used
@@ -154,3 +164,11 @@ didn't know about it! although technically that reads registers
    of the desired 32-bit integer is 0.  (A better way to construct a 32-bit
    integer is to use pli (extended mnemonic for paddi).)
 **
+
+it is extremely unlikely that we (Libre-SOC) will implement any of v3.1
+64-bit prefixing (it cannot be Vectorised, resulting unacceptably in
+96-bit instructions so what is the point). that said the LD
+addressing immediate extended range is extremely useful.
+
+bottom line we have given almost no thought to using any v3.1 Scalar
+Prefixed instructions, at all, so don't even know 99% of what they do.
-- 
2.30.2