From a2dba29155bb1f6e4f128bc64b4c4aba1747063b Mon Sep 17 00:00:00 2001 From: David Edelsohn Date: Wed, 17 Aug 2005 19:12:16 -0400 Subject: [PATCH] rs6000.md (leu): Convert to mode macro. * config/rs6000/rs6000.md (leu): Convert to mode macro. (leu_compare): Same. (plus_leu): Same. (neg_leu): Same. (and_neg_leu_compare): Same. (plus_ltu): Same. (geu): Same. (geu_compare): Same. (plus_geu): Same. (neg_geu): Same. (and_neg_geu): Same. (plus_gt): Same. (gtu_compare): Same. (plus_gtu): Same. From-SVN: r103233 --- gcc/ChangeLog | 20 +- gcc/config/rs6000/rs6000.md | 385 +++++++++++------------------------- 2 files changed, 137 insertions(+), 268 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b2785edd6f3..54d2fac793f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,21 @@ +2005-08-17 David Edelsohn + + * config/rs6000/rs6000.md (leu): Convert to mode macro. + (leu_compare): Same. + (plus_leu): Same. + (neg_leu): Same. + (and_neg_leu_compare): Same. + (plus_ltu): Same. + (geu): Same. + (geu_compare): Same. + (plus_geu): Same. + (neg_geu): Same. + (and_neg_geu): Same. + (plus_gt): Same. + (gtu_compare): Same. + (plus_gtu): Same. + 2005-08-17 Erik Christiansen * config/v850/lib1funcs.asm (callt_save_interrupt): Fix comment typos. @@ -18,7 +36,7 @@ 2005-08-17 J"orn Rennecke - * varasm.c (decode_reg_name): Skip empty aqdditional register names. + * varasm.c (decode_reg_name): Skip empty additional register names. 2005-08-16 Zdenek Dvorak diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8ed55f4ad92..ad7beba6d26 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -11658,64 +11658,24 @@ {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" [(set_attr "length" "12")]) -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "reg_or_short_operand" "rI")))] - "TARGET_32BIT" +(define_insn "*leu" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (leu:P (match_operand:P 1 "gpc_reg_operand" "r") + (match_operand:P 2 "reg_or_short_operand" "rI")))] + "" "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" [(set_attr "type" "three") (set_attr "length" "12")]) -(define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") - (match_operand:DI 2 "reg_or_short_operand" "rI")))] - "TARGET_64BIT" - "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" - [(set_attr "type" "three") - (set_attr "length" "12")]) - -(define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC - (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (leu:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT" - "@ - subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 - #" - [(set_attr "type" "compare") - (set_attr "length" "12,16")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC - (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_short_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (leu:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT && reload_completed" - [(set (match_dup 0) - (leu:DI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_insn "" +(define_insn "*leu_compare" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC - (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) + (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r") + (match_operand:P 2 "reg_or_short_operand" "rI,rI")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (leu:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT" + (set (match_operand:P 0 "gpc_reg_operand" "=r,r") + (leu:P (match_dup 1) (match_dup 2)))] + "" "@ {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 #" @@ -11725,25 +11685,25 @@ (define_split [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC - (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_short_operand" "")) + (leu:P (match_operand:P 1 "gpc_reg_operand" "") + (match_operand:P 2 "reg_or_short_operand" "")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (leu:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT && reload_completed" + (set (match_operand:P 0 "gpc_reg_operand" "") + (leu:P (match_dup 1) (match_dup 2)))] + "reload_completed" [(set (match_dup 0) - (leu:SI (match_dup 1) (match_dup 2))) + (leu:P (match_dup 1) (match_dup 2))) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") - (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gpc_reg_operand" "r")))] - "TARGET_32BIT" +(define_insn "*plus_leu" + [(set (match_operand:P 0 "gpc_reg_operand" "=&r") + (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r") + (match_operand:P 2 "reg_or_short_operand" "rI")) + (match_operand:P 3 "gpc_reg_operand" "r")))] + "" "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" [(set_attr "type" "two") (set_attr "length" "8")]) @@ -11813,22 +11773,22 @@ (const_int 0)))] "") -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "reg_or_short_operand" "rI"))))] - "TARGET_32BIT" +(define_insn "*neg_leu" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r") + (match_operand:P 2 "reg_or_short_operand" "rI"))))] + "" "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" [(set_attr "type" "three") (set_attr "length" "12")]) -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") - (and:SI (neg:SI - (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "reg_or_short_operand" "rI"))) - (match_operand:SI 3 "gpc_reg_operand" "r")))] - "TARGET_32BIT" +(define_insn "*and_neg_leu" + [(set (match_operand:P 0 "gpc_reg_operand" "=&r") + (and:P (neg:P + (leu:P (match_operand:P 1 "gpc_reg_operand" "r") + (match_operand:P 2 "reg_or_short_operand" "rI"))) + (match_operand:P 3 "gpc_reg_operand" "r")))] + "" "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" [(set_attr "type" "three") (set_attr "length" "12")]) @@ -12035,15 +11995,15 @@ (set (match_dup 0) (neg:P (match_dup 0)))] "") -(define_insn "" +(define_insn "*ltu_compare" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") (compare:CC - (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) + (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (ltu:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT" + (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") + (ltu:P (match_dup 1) (match_dup 2)))] + "" "@ {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 @@ -12055,41 +12015,29 @@ (define_split [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC - (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_neg_short_operand" "")) + (ltu:P (match_operand:P 1 "gpc_reg_operand" "") + (match_operand:P 2 "reg_or_neg_short_operand" "")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ltu:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT && reload_completed" + (set (match_operand:P 0 "gpc_reg_operand" "") + (ltu:P (match_dup 1) (match_dup 2)))] + "reload_completed" [(set (match_dup 0) - (ltu:SI (match_dup 1) (match_dup 2))) + (ltu:P (match_dup 1) (match_dup 2))) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") -(define_insn_and_split "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") - (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) - (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] - "TARGET_32BIT" - "#" - "&& !reg_overlap_mentioned_p (operands[0], operands[3])" - [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2)))) - (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))] - "") - -(define_insn_and_split "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") - (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")) - (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))] - "TARGET_64BIT" +(define_insn_and_split "*plus_ltu" + [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r") + (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r") + (match_operand:P 2 "reg_or_neg_short_operand" "r,P")) + (match_operand:P 3 "reg_or_short_operand" "rI,rI")))] + "" "#" "&& !reg_overlap_mentioned_p (operands[0], operands[3])" - [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2)))) - (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))] + [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2)))) + (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))] "") (define_insn "" @@ -12297,37 +12245,26 @@ "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" [(set_attr "length" "12")]) -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] - "TARGET_32BIT" +(define_insn "*geu" + [(set (match_operand:P 0 "gpc_reg_operand" "=r,r") + (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") + (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))] + "" "@ {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" [(set_attr "type" "three") (set_attr "length" "12")]) -(define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] - "TARGET_64BIT" - "@ - subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 - addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" - [(set_attr "type" "three") - (set_attr "length" "12")]) - -(define_insn "" +(define_insn "*geu_compare" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") (compare:CC - (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) + (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (geu:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT" + (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") + (geu:P (match_dup 1) (match_dup 2)))] + "" "@ {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 @@ -12339,58 +12276,25 @@ (define_split [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC - (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_neg_short_operand" "")) + (geu:P (match_operand:P 1 "gpc_reg_operand" "") + (match_operand:P 2 "reg_or_neg_short_operand" "")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (geu:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT && reload_completed" - [(set (match_dup 0) - (geu:SI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC - (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (geu:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT" - "@ - subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 - addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 - # - #" - [(set_attr "type" "compare") - (set_attr "length" "12,12,16,16")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC - (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_neg_short_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (geu:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT && reload_completed" + (set (match_operand:P 0 "gpc_reg_operand" "") + (geu:P (match_dup 1) (match_dup 2)))] + "reload_completed" [(set (match_dup 0) - (geu:DI (match_dup 1) (match_dup 2))) + (geu:P (match_dup 1) (match_dup 2))) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") - (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) - (match_operand:SI 3 "gpc_reg_operand" "r,r")))] - "TARGET_32BIT" +(define_insn "*plus_geu" + [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r") + (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") + (match_operand:P 2 "reg_or_neg_short_operand" "r,P")) + (match_operand:P 3 "gpc_reg_operand" "r,r")))] + "" "@ {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" @@ -12466,24 +12370,24 @@ (const_int 0)))] "") -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] - "TARGET_32BIT" +(define_insn "*neg_geu" + [(set (match_operand:P 0 "gpc_reg_operand" "=r,r") + (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") + (match_operand:P 2 "reg_or_short_operand" "r,I"))))] + "" "@ {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" [(set_attr "type" "three") (set_attr "length" "12")]) -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") - (and:SI (neg:SI - (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) - (match_operand:SI 3 "gpc_reg_operand" "r,r")))] - "TARGET_32BIT" +(define_insn "*and_neg_geu" + [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r") + (and:P (neg:P + (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") + (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))) + (match_operand:P 3 "gpc_reg_operand" "r,r")))] + "" "@ {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" @@ -12563,7 +12467,7 @@ (const_int 0)))] "") -(define_insn "" +(define_insn "*gt0si" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)))] @@ -12572,7 +12476,7 @@ [(set_attr "type" "three") (set_attr "length" "12")]) -(define_insn "" +(define_insn "*gt0di" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") (const_int 0)))] @@ -12682,26 +12586,16 @@ (const_int 0)))] "") -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") - (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") - (const_int 0)) - (match_operand:SI 2 "gpc_reg_operand" "r")))] - "TARGET_32BIT" +(define_insn "*plus_gt" + [(set (match_operand:P 0 "gpc_reg_operand" "=&r") + (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r") + (const_int 0)) + (match_operand:P 2 "gpc_reg_operand" "r")))] + "" "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" [(set_attr "type" "three") (set_attr "length" "12")]) -(define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") - (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") - (const_int 0)) - (match_operand:DI 2 "gpc_reg_operand" "r")))] - "TARGET_64BIT" - "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" - [(set_attr "type" "three") - (set_attr "length" "12")]) - (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC @@ -12942,15 +12836,15 @@ (set (match_dup 0) (neg:P (match_dup 0)))] "") -(define_insn "" +(define_insn "*gtu_compare" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC - (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) + (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r") + (match_operand:P 2 "reg_or_short_operand" "rI,rI")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (gtu:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT" + (set (match_operand:P 0 "gpc_reg_operand" "=r,r") + (gtu:P (match_dup 1) (match_dup 2)))] + "" "@ {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 #" @@ -12960,72 +12854,29 @@ (define_split [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC - (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_short_operand" "")) + (gtu:P (match_operand:P 1 "gpc_reg_operand" "") + (match_operand:P 2 "reg_or_short_operand" "")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (gtu:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT && reload_completed" - [(set (match_dup 0) - (gtu:SI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC - (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (gtu:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT" - "@ - subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 - #" - [(set_attr "type" "compare") - (set_attr "length" "12,16")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC - (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_short_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (gtu:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT && reload_completed" + (set (match_operand:P 0 "gpc_reg_operand" "") + (gtu:P (match_dup 1) (match_dup 2)))] + "reload_completed" [(set (match_dup 0) - (gtu:DI (match_dup 1) (match_dup 2))) + (gtu:P (match_dup 1) (match_dup 2))) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") -(define_insn_and_split "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") - (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "reg_or_short_operand" "rI")))] - "TARGET_32BIT" - "#" - "&& !reg_overlap_mentioned_p (operands[0], operands[3])" - [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2)))) - (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))] - "") - -(define_insn_and_split "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") - (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") - (match_operand:DI 2 "reg_or_short_operand" "rI")) - (match_operand:DI 3 "reg_or_short_operand" "rI")))] - "TARGET_64BIT" +(define_insn_and_split "plus_gtu" + [(set (match_operand:P 0 "gpc_reg_operand" "=&r") + (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r") + (match_operand:P 2 "reg_or_short_operand" "rI")) + (match_operand:P 3 "reg_or_short_operand" "rI")))] + "" "#" "&& !reg_overlap_mentioned_p (operands[0], operands[3])" - [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2)))) - (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))] + [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) + (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))] "") (define_insn "" -- 2.30.2