From a2fc3fb579fb9144b6bf4facc19e7241cb71b3c2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 23 Jun 2021 18:57:22 +0100 Subject: [PATCH] add start of bit-reverse mode for LD/ST to SVP64 encode/decode --- src/openpower/consts.py | 3 ++- src/openpower/decoder/power_enums.py | 1 + src/openpower/decoder/power_svp64_rm.py | 12 +++++++++--- src/openpower/sv/trans/svp64.py | 7 +++++++ 4 files changed, 19 insertions(+), 4 deletions(-) diff --git a/src/openpower/consts.py b/src/openpower/consts.py index 3cc9e08a..5c60bd97 100644 --- a/src/openpower/consts.py +++ b/src/openpower/consts.py @@ -222,6 +222,7 @@ class SVP64MODEb: # mode bits MOD2_MSB = 0 MOD2_LSB = 1 + LDST_BITREV = 2 # set =1 for bitreverse mode # when predicate not set: 0=ignore/skip 1=zero DZ = 3 # for destination SZ = 4 # for source @@ -239,7 +240,7 @@ class SVP64MODEb: CR_LSB = 4 RC1 = 4 # update CR as if Rc=1 (when Rc=0) # LD immediate els (element-stride) locations, depending on mode - ELS_NORMAL = 2 + ELS_NORMAL = 4 ELS_FFIRST_PRED = 3 ELS_SAT = 4 # BO bits diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index 22121cce..0788642b 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -212,6 +212,7 @@ class SVP64LDSTmode(Enum): INDEXED = 1 ELSTRIDE = 2 UNITSTRIDE = 3 + BITREVERSE = 4 # supported instructions: make sure to keep up-to-date with CSV files diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py index 6082a8fb..c052924d 100644 --- a/src/openpower/decoder/power_svp64_rm.py +++ b/src/openpower/decoder/power_svp64_rm.py @@ -42,7 +42,8 @@ https://libre-soc.org/openpower/sv/svp64/ https://libre-soc.org/openpower/sv/ldst/ LD/ST immed: -00 els sz dz normal mode +00 0 dz els normal mode (with element-stride) +00 1 dz rsvd bit-reversed mode 01 inv CR-bit Rc=1: ffirst CR sel 01 inv els RC1 Rc=0: ffirst z/nonz 10 N dz els sat mode: N=0/1 u/s @@ -135,7 +136,9 @@ class SVP64RMModeDecode(Elaboratable): with m.Switch(mode2): with m.Case(0): # needs further decoding (LDST no mapreduce) with m.If(is_ldst): - comb += self.pred_sz.eq(mode[SVP64MODE.SZ]) + # XXX TODO, work out which of these is most appropriate + # set both? or just the one? or one if LD, the other if ST? + comb += self.pred_sz.eq(mode[SVP64MODE.DZ]) comb += self.pred_dz.eq(mode[SVP64MODE.DZ]) with m.Elif(mode[SVP64MODE.REDUCE]): with m.If(self.rm_in.subvl == Const(0, 2)): # no SUBVL @@ -179,8 +182,11 @@ class SVP64RMModeDecode(Elaboratable): with m.If(self.rc_in): comb += els.eq(mode[SVP64MODE.ELS_FFIRST_PRED]) + # Bit-reversed Mode + with m.If(mode[SVP64MODE.LDST_BITREV]): + comb += self.ldstmode.eq(SVP64LDSTmode.BITREVERSE) # RA is vectorised - with m.If(self.ldst_ra_vec): + with m.Elif(self.ldst_ra_vec): comb += self.ldstmode.eq(SVP64LDSTmode.INDEXED) # not element-strided, therefore unit... with m.Elif(~els): diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 2bfe4c2b..c1fca225 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -481,6 +481,7 @@ class SVP64Asm: mapreduce = False reverse_gear = False + bitreverse = False mapreduce_crm = False mapreduce_svm = False @@ -509,6 +510,9 @@ class SVP64Asm: smmode, smask = decode_predicate(encmode[3:]) mmode = smmode has_smask = True + # bitreverse LD/ST + elif encmode.startswith("br"): + bitreverse = True # vec2/3/4 elif encmode.startswith("vec"): subvl = decode_subvl(encmode[3:]) @@ -614,6 +618,9 @@ class SVP64Asm: if is_ldst: # TODO: for now, LD/ST-indexed is ignored. mode |= ldst_elstride << SVP64MODE.ELS_NORMAL # element-strided + # bitreverse mode + if bitreverse: + mode |= 1 << SVP64MODE.LDST_BITREV else: # TODO, reduce and subvector mode # 00 1 dz CRM reduce mode (mapreduce), SUBVL=1 -- 2.30.2