From a305d205f71a1b1ba046077d3f46ab904a7d545d Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 12 Apr 2021 16:15:38 +0000
Subject: [PATCH] add FreePDK45 variant of experiments10_verilog

---
 experiments10_verilog/freepdk_c4m45/Makefile  | 44 +++++++++++++++
 .../freepdk_c4m45/build_full.sh               | 34 ++++++++++++
 .../freepdk_c4m45/design-flow.mk              | 55 +++++++++++++++++++
 experiments10_verilog/freepdk_c4m45/mksym.sh  | 46 ++++++++++++++++
 .../freepdk_c4m45/netlists.txt                |  5 ++
 mksym.sh                                      |  6 +-
 6 files changed, 189 insertions(+), 1 deletion(-)
 create mode 100755 experiments10_verilog/freepdk_c4m45/Makefile
 create mode 100755 experiments10_verilog/freepdk_c4m45/build_full.sh
 create mode 100644 experiments10_verilog/freepdk_c4m45/design-flow.mk
 create mode 100755 experiments10_verilog/freepdk_c4m45/mksym.sh
 create mode 100644 experiments10_verilog/freepdk_c4m45/netlists.txt

diff --git a/experiments10_verilog/freepdk_c4m45/Makefile b/experiments10_verilog/freepdk_c4m45/Makefile
new file mode 100755
index 0000000..72c1116
--- /dev/null
+++ b/experiments10_verilog/freepdk_c4m45/Makefile
@@ -0,0 +1,44 @@
+
+        LOGICAL_SYNTHESIS = Yosys
+       PHYSICAL_SYNTHESIS = Coriolis
+               DESIGN_KIT = FreePDK_C4M45
+            YOSYS_FLATTEN = No
+                     CHIP = chip
+                     CORE = add
+            USE_CLOCKTREE = Yes
+                USE_DEBUG = No
+                 USE_KITE = No
+                  RM_CHIP = Yes
+
+                 NETLISTS = $(shell cat netlists.txt)
+#                PATTERNS = add_r
+
+
+ include ./mk/design-flow.mk
+
+# generate verilog file from python nmigen command
+add.v: add.py
+	python3 add.py
+
+chip_r.vst: add.vst
+	-$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
+
+chip_r.ap: chip_r.vst
+
+
+blif:      add.blif
+vst:       add.vst
+
+lvx:       lvx-chip_r
+druc:      druc-chip_r
+dreal:     dreal-chip_r
+flatph:    flatph-chip_r
+view:      cgt-chip_r
+
+layout:    chip_r.ap
+gds:       chip_r.gds
+gds_flat:  chip_r_flat.gds
+cif:  	   chip_r.cif
+
+view:      cgt-chip_r
+sim:       asimut-add_r
diff --git a/experiments10_verilog/freepdk_c4m45/build_full.sh b/experiments10_verilog/freepdk_c4m45/build_full.sh
new file mode 100755
index 0000000..67dd695
--- /dev/null
+++ b/experiments10_verilog/freepdk_c4m45/build_full.sh
@@ -0,0 +1,34 @@
+#!/bin/sh
+
+# full core build including QTY 4of 4k SRAMs: please remember to alter
+# doDesign.py before running!
+# change the settings to the larger chip/corona size
+echo "remember to check doDesign core size"
+
+pdk=`realpath ../../c4m-pdk-freepdk45`
+export NDA_TOP=${pdk}/coriolis/techno
+
+# initialise/update the pinmux & c4m-pdk-freepdk45 submodule
+#pushd ..
+git submodule update --init --remote
+#popd
+
+# makes symlinks to alliance
+./mksym.sh
+touch mk/users.d/user-${USER}.mk
+rm -f mk/design-flow.mk
+cp design-flow.mk mk/
+lib=${pdk}/views/FreePDK45/FlexLib/liberty/FlexLib_nom.lib
+echo "export REAL_MODE = Yes" > mk/dks.d/FreePDK_C4M45.mk
+echo "export LIBERTY_FILE = $lib" >> mk/dks.d/FreePDK_C4M45.mk
+
+# clear out
+make clean
+rm *.vst *.ap *.v
+
+# make the vst from ilang
+make vst
+
+# starts the build.
+make lvx
+
diff --git a/experiments10_verilog/freepdk_c4m45/design-flow.mk b/experiments10_verilog/freepdk_c4m45/design-flow.mk
new file mode 100644
index 0000000..e8b0d12
--- /dev/null
+++ b/experiments10_verilog/freepdk_c4m45/design-flow.mk
@@ -0,0 +1,55 @@
+
+ include ./mk/os.mk
+ include ./mk/users.mk
+ include ./mk/binaries.mk
+ include ./mk/alliance.mk
+
+# Some useful functions.
+ run_if_older = if [ \( ! -e "$(1)" \) -o \( "$(1)" -ot "$(2)" \) ]; then $(3); else echo "\"$(1)\" newer than \"$(2)\" (skip rule)."; fi 
+
+# Select the Design Kit.
+ ifeq ($(DESIGN_KIT),sxlib)
+   include ./mk/dks.d/sxlib.mk
+ else ifeq ($(DESIGN_KIT),nsxlib)
+   include ./mk/dks.d/nsxlib.mk
+ else ifeq ($(DESIGN_KIT),nsxlib45)
+   include ./mk/dks.d/nsxlib45.mk
+ else ifeq ($(DESIGN_KIT),Hibikino)
+   include ./mk/dks.d/sxlib-hibikino.mk
+ else ifeq ($(DESIGN_KIT),FreePDK_45)
+   include ./mk/dks.d/FreePDK_45.mk
+ else ifeq ($(DESIGN_KIT),phenitec06)
+   include ./mk/dks.d/phenitec06.mk
+ else ifeq ($(DESIGN_KIT),cmos45)
+   include ./mk/dks.d/nsxlib45.mk
+ else ifeq ($(DESIGN_KIT),c35b4)
+   include ./mk/dks.d/c35b4.mk
+ else ifeq ($(DESIGN_KIT),FlexLib018)
+   include ./mk/dks.d/FlexLib018.mk
+ else ifeq ($(DESIGN_KIT),FreePDK_C4M45)
+   include ./mk/dks.d/FreePDK_C4M45.mk
+ else
+   $(error DESIGN_KIT variable has not been set or has an unsupported value)
+ endif
+
+# Select the logical synthesis tools.
+ ifeq ($(LOGICAL_SYNTHESIS),Yosys)
+   include ./mk/synthesis-yosys.mk
+ else ifeq ($(LOGICAL_SYNTHESIS),Alliance)
+   include ./mk/synthesis-alliance.mk
+ else
+   include ./mk/synthesis-disabled.mk
+ endif
+
+# Select the physical synthesis tools.
+ ifeq ($(PHYSICAL_SYNTHESIS),Coriolis)
+   include ./mk/pr-coriolis.mk
+ else ifeq ($(PHYSICAL_SYNTHESIS),Alliance)
+   include ./mk/pr-alliance.mk
+ else ifeq ($(PHYSICAL_SYNTHESIS),Hibikino)
+   include ./mk/pr-hibikino.mk
+ else
+   $(error PHYSICAL_SYNTHESIS variable has not been set or has an unsupported value)
+ endif
+
+ $(info Using RDS_TECHNO_NAME = "${RDS_TECHNO_NAME}")
diff --git a/experiments10_verilog/freepdk_c4m45/mksym.sh b/experiments10_verilog/freepdk_c4m45/mksym.sh
new file mode 100755
index 0000000..1659db8
--- /dev/null
+++ b/experiments10_verilog/freepdk_c4m45/mksym.sh
@@ -0,0 +1,46 @@
+#!/bin/bash
+
+ALLIANCE_TOOLKIT=${ALLIANCE_TOOLKIT:-${HOME}/alliance-check-toolkit/}
+if [ ! -d ${ALLIANCE_TOOLKIT} ]; then
+  echo "alliance-check-toolkit not found; please set ALLIANCE_TOOLKIT"
+  exit 20
+fi
+
+echo "creating symlinks"
+
+mkdir -p mk/dks.d
+mkdir -p mk/users.d
+
+declare -a ScriptsArray=("os" "users" "binaries" "alliance"
+        "design-flow" "pr-coriolis" "pr-alliance" "pr-hibikino"
+	"synthesis-yosys"
+)
+
+for script in "${ScriptsArray[@]}"; do
+    if [ ! -L "mk/$script.mk" ]; then
+        echo "link" mk/$script.mk
+        ln -s $ALLIANCE_TOOLKIT/etc/mk/$script.mk mk/$script.mk
+    fi
+done
+
+declare -a LibsArray=("sxlib" "nsxlib" "nsxlib45" "cmos" "cmos45" "mosis"
+)
+
+for script in "${LibsArray[@]}"; do
+    if [ ! -L "mk/dks.d/$script.mk" ]; then
+        echo "link" mk/dks.d/$script.mk
+        ln -s $ALLIANCE_TOOLKIT/etc/mk/dks.d/$script.mk mk/dks.d/$script.mk
+    fi
+done
+
+declare -a UsersArray=("lkcl"
+)
+
+for script in "${UsersArray[@]}"; do
+    if [ ! -L "mk/users.d/user-$script.mk" ]; then
+        echo "link" mk/users.d/user-$script.mk
+        ln -s $ALLIANCE_TOOLKIT/etc/mk/users.d/user-$script.mk \
+		mk/users.d/user-$script.mk
+    fi
+done
+
diff --git a/experiments10_verilog/freepdk_c4m45/netlists.txt b/experiments10_verilog/freepdk_c4m45/netlists.txt
new file mode 100644
index 0000000..599bb5a
--- /dev/null
+++ b/experiments10_verilog/freepdk_c4m45/netlists.txt
@@ -0,0 +1,5 @@
+add
+fsm
+idblock
+irblock
+jtag
diff --git a/mksym.sh b/mksym.sh
index 1865ad0..1659db8 100755
--- a/mksym.sh
+++ b/mksym.sh
@@ -1,6 +1,10 @@
 #!/bin/bash
 
 ALLIANCE_TOOLKIT=${ALLIANCE_TOOLKIT:-${HOME}/alliance-check-toolkit/}
+if [ ! -d ${ALLIANCE_TOOLKIT} ]; then
+  echo "alliance-check-toolkit not found; please set ALLIANCE_TOOLKIT"
+  exit 20
+fi
 
 echo "creating symlinks"
 
@@ -19,7 +23,7 @@ for script in "${ScriptsArray[@]}"; do
     fi
 done
 
-declare -a LibsArray=("sxlib" "nsxlib" "nsxlib45" "cmos" "mosis" "cmos45"
+declare -a LibsArray=("sxlib" "nsxlib" "nsxlib45" "cmos" "cmos45" "mosis"
 )
 
 for script in "${LibsArray[@]}"; do
-- 
2.30.2