From a3097ba93ed558d704c0e4eb11b93d08f532bf65 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 14 Feb 2021 12:34:38 +0000 Subject: [PATCH] add extra FSM explanatory comments to TestIssuer --- src/soc/simple/issuer.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index ad9b1dd7..8c69b115 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -260,6 +260,11 @@ class TestIssuerInternal(Elaboratable): # then "holds" information, combinatorially, for the core # (as opposed to using sync - which would be on a clock's delay) # this includes the actual opcode, valid flags and so on. + + # this FSM performs fetch of raw instruction data, partial-decodes + # it 32-bit at a time to detect SVP64 prefixes, and will optionally + # read a 2nd 32-bit quantity if that occurs. + with m.FSM(name='fetch_fsm'): # waiting (zzz) @@ -335,7 +340,11 @@ class TestIssuerInternal(Elaboratable): with m.If(fetch_insn_ready_i): m.next = "IDLE" - # decode / issue / execute FSM + # decode / issue / execute FSM. this interacts with the "fetch" FSM + # through fetch_pc_ready/valid (incoming) and fetch_insn_ready/valid + # (outgoing). SVP64 RM prefixes have already been set up by the + # "fetch" phase, so execute is fairly straightforward. + with m.FSM(): # go fetch the instruction at the current PC -- 2.30.2