From a35d3ff167a50bcbaeffbefc46bde5f640a475f5 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 22 Apr 2013 13:20:33 -0400 Subject: [PATCH] mem: Add a WideIO DRAM configuration This patch adds a WideIO 200 MHz configuration that can be used as a baseline to compare with DDRx and LPDDRx. Note that it is a single channel and that it should be replicated 4 times. It is based on publically available information and attempts to capture an envisioned 8 Gbit single-die part (i.e. without TSVs). --- src/mem/SimpleDRAM.py | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/src/mem/SimpleDRAM.py b/src/mem/SimpleDRAM.py index 60bc1cffb..864ddfc31 100644 --- a/src/mem/SimpleDRAM.py +++ b/src/mem/SimpleDRAM.py @@ -239,3 +239,39 @@ class SimpleLPDDR2_S4(SimpleDRAM): # Irrespective of size, tFAW is 50 ns tXAW = '50ns' activation_limit = 4 + +# High-level model of a single WideIO x128 interface (one command and +# address bus), with default timings based on an estimated WIO-200 8 +# Gbit part. +class SimpleWideIO(SimpleDRAM): + # Assuming 64 byte cache lines, use a 4kbyte page size, this + # depends on the memory density + lines_per_rowbuffer = 64 + + # Use one rank for a one-high die stack + ranks_per_channel = 1 + + # WideIO has 4 banks in all configurations + banks_per_rank = 4 + + # WIO-200 + tRCD = '18ns' + tCL = '18ns' + tRP = '18ns' + + # Assuming 64 byte cache lines, across an x128 SDR interface, + # translates to BL4, 4 clocks @ 200 MHz + tBURST = '20ns' + + # WIO 8 Gb + tRFC = '210ns' + + # WIO 8 Gb, <=85C, half for >85C + tREFI = '3.9us' + + # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns + tWTR = '15ns' + + # Two instead of four activation window + tXAW = '50ns' + activation_limit = 2 -- 2.30.2